Date: Thursday 17 March 2016
Time: 16:00 - 17:30
Location / Room: Konferenz 2

Chair:
Graziano Pravadelli, Universita degli Studi di Verona, IT

Co-Chair:
Valeria Bertacco, University of Michigan, US

The session deals with several facets of simulation optimization, ranging from timing, circuit, and instruction decoding.

Time	Label	Presentation Title Authors
16:00	12.4.1	ACCELERATING SOURCE-LEVEL TIMING SIMULATION Speaker: Oliver Bringmann, Universität Tübingen, DE Authors: Simon Schulz1 and Oliver Bringmann2 1Universität Tübingen, DE; 2Universität Tübingen / FZI, DE Abstract Abstract—Source-level timing simulation (SLTS) is a promising method to overcome one major challenge in early and rapid prototyping: fast and accurate simulation of timing behavior. However, most of existing SLTS approaches are still coupled with a considerable simulation overhead. We present a method to reduce source-level timing simulation overhead by removing superfluous instrumentation based on instrumentation dependency graphs. We show in experiments, that our optimizations decrease simulation overhead significantly (up to factor 7.7), without losing accuracy. Our detailed experiments are based on benchmarks as well as real life production code, that is simulated in a virtual environment. Download Paper (PDF; Only available from the DATE venue WiFi)
16:30	12.4.2	SPARSITY-ORIENTED SPARSE SOLVER DESIGN FOR CIRCUIT SIMULATION Speaker: Xiaoming Chen, Tsinghua University, CN Authors: Xiaoming Chen, Lixue Xia, Yu Wang and Huazhong Yang, Tsinghua University, CN Abstract The sparse solver is a critical component in circuit simulators. The widely used solver KLU is based on a pure column-level algorithm. In this paper, we point out that KLU is not always the best algorithm for circuit matrices by experiments. We also demonstrate that the optimal algorithm strongly depends on the sparsity of the matrix. Two sparse LU factorization algorithms are proposed for extremely sparse matrices and dense matrices. A simple but effective strategy is proposed to select the optimal algorithm according to the sparsity. By combining the two new algorithms and the selection method together, the proposed solver achieves much higher performance than both KLU and PARDISO. Download Paper (PDF; Only available from the DATE venue WiFi)
17:00	12.4.3	INTEGRATION OF MIXED-SIGNAL COMPONENTS INTO VIRTUAL PLATFORMS FOR HOLISTIC SIMULATION OF SMART SYSTEMS Speaker: Davide Quaglia, University of Verona, IT Authors: Enrico Fraccaroli1, Michele Lora1, Sara Vinco2, Davide Quaglia1 and Franco Fummi1 1University of Verona, IT; 2Politecnico di Torino, IT Abstract Nowadays, the design of applications based on smart systems requires the joint simulation of both digital and analog aspects. Even if analog-mixed-signal (AMS) extensions of hardware description languages are an enabling factor, they do not provide a general methodology for the integration of AMS models into digital virtual platforms. This paper defines the problem and provides two main contributions: 1) the automatic conversion of analog models from Verilog-AMS to C++/SystemC, to remove the overhead of co-simulation with traditional virtual platform tools, and 2) the automatic abstraction of analog conservative models, with the goal of increasing simulation speed. Experimental results show that the virtual platform with automatically integrated analog components is 40 times faster than co-simulation with Verilog-AMS, and the increase of speed due to abstraction is more than 100%. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	12.4.4	DECISION TREE GENERATION FOR DECODING IRREGULAR INSTRUCTIONS Speaker: Katsumi Okuda, Mitsubishi Electric Corporation, JP Authors: Katsumi Okuda and Haruhiko Takeyama, Mitsubishi Electric Corporation, JP Abstract Instruction set simulators (ISS) are indispensable tools for the development of new architectures and embedded software. One essential part of any ISS is its instruction decoder. Since manual implementation of an instruction decoder for a complex instruction set is tedious and error-prone, automatic generation of an instruction decoder is required. However, as a result of the increasing irregularity of instruction encoding because of the incremental addition of instructions, generating efficient instruction decoders is complicated. In this paper, we propose a generation algorithm of a decision tree for decoding irregular instructions. Our algorithm can generate decision trees by using not only significant bits of opcode patterns but also exclusion conditions in decoding entries. Our results on ARM, Thumb-2, MIPS64, RH850, and TriCore show that our algorithm generates efficient instruction decoders in terms of both depth and memory consumption regardless of whether the target instruction set is irregular or not. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30		End of session