11.2 Beating New Technology Paths for NoC

Time	Label	Presentation Title Authors
14:00	11.2.1	CROSS-LAYER FLOORPLAN OPTIMIZATION FOR SILICON PHOTONIC NOCS IN MANY-CORE SYSTEMS Speaker: Ayse Coskun, Boston University, US Authors: Ayse Coskun¹, Anjun Gu², Warren Jin³, Ajay Jayant Joshi¹, Andrew B. Kahng², Jonathan Klamkin³, Yenai Ma¹, John Recchio², Vaishnav Srinivas² and Tiansheng Zhang¹ ¹Boston University, US; ²University of California, San Diego, US; ³UC Santa Barbara, US Abstract Many-core chip architectures are now feasible, but the power consumption of electrical networks-on-chip does not scale well. Silicon photonic NoCs (PNoCs) are more scalable and power efficient, but floorplan optimization is challenging. Prior work optimizes PNoC floorplans through simultaneous place and route, but does not address cross-layer effects that span optical and electrical boundaries, chip thermal profiles, or effects of job scheduling policies. This paper proposes a more comprehensive, cross-layer optimization of the silicon PNoC and core cluster floorplan. Our simultaneous placement (locations of router groups and core clusters) and routing (waveguide layout) considers scheduling policy, thermal tuning, and heterogeneity in chip power profiles. The core of our optimizer is a mixed-integer linear programming formulation that minimizes NoC power, including (1) laser source power due to propagation, bend and crossing losses; (2) electrical and electrical-optical-electrical conversion power; and (3) thermal tuning power. Our experiments vary numbers of cores, optical data rate per wavelength, number of waveguides and other parameters to investigate scalability and tradeoffs through a large design space. We demonstrate how the optimal floorplan changes with cross-layer awareness: metrics of interest such as optimal waveguide length or thermal tuning power change significantly (up to 4X) based on power and utilization levels of cores, chip and cluster aspect ratio, and laser source sharing mechanism. Exploration of a large solution space is achieved with reasonable runtimes, and is perfectly parallelizable. Our optimizer thus affords designers with more accurate, cross-layer chip planning decision support to accelerate adoption of PNoC-based solutions. Download Paper (PDF; Only available from the DATE venue WiFi)
14:30	11.2.2	ADAPTIVE MULTI-VOLTAGE SCALING IN WIRELESS NOC FOR HIGH PERFORMANCE LOW POWER APPLICATIONS Speaker: Sujay Deb, IIIT Delhi, IN Authors: Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore and Sujay Deb, IIIT Delhi, IN Abstract Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi hop long distance communication bottlenecks and opens up innumerable possibilities of topological innovations that are not possible otherwise. However, energy consumption in routers along with Wireless Interface (WI) components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure (routers, links, WIs). The usage of the routers and WIs are application dependent and for most cases performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable systems that can switch between both high performance and low power modes can cater to wide range of applications. In this paper, we propose a novel design methodology for energy efficient WNoC using Adaptive Multi-voltage Scaling (AMS) that reduces dynamic power consumption, along with power gating to prevent static power dissipation in routers and WIs. We evaluate our proposed design in presence of real and synthetic traffic patterns. This approach saves up to 62.50% of static power with less than 1% area overhead. In different traffic scenarios, the proposed WNoC reduces overall packet energy dissipation by 35% on average compared to a regular WNoC, without significant performance degradation. Design considerations for augmenting existing WNoCs with these routers and corresponding overheads are also presented. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	11.2.3	ENERGY EFFICIENT TRANSCEIVER IN WIRELESS NETWORK ON CHIP ARCHITECTURES Speaker: Davide Patti, University of Catania, IT Authors: Vincenzo Catania¹, Andrea Mineo¹, Salvatore Monteleone¹, Maurizio Palesi² and Davide Patti¹ ¹University of Catania, IT; ²Kore University, IT Abstract The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs, account for a significant fraction of the total communication energy budget. In this paper, we propose a novel energy management scheme aimed at improving the energy efficiency of a WiNoC architecture based on the selective disabling of the power hungry modules that are predicted being not used during the forthcoming clock cycles. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	IP5-9, 115	PRADA: COMBATING VOLTAGE NOISE IN THE NOC POWER SUPPLY THROUGH FLOW-CONTROL AND ROUTING ALGORITHMS Speaker: Prabal Basu, Utah State University, US Authors: Prabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty and Sanghamitra Roy, Utah State University, US Abstract Network-on-Chip (NoC) has become the de-facto standard for on-chip communication in MPSoCs. The growing NoC power footprint, increase in the transistor current, and high switching speed of the logic devices, exacerbate the peak power supply noise (PSN) in the NoC power delivery network (PDN). Hence, preserving power supply integrity in the NoC PDN is critical. In this work, we propose PRADA (PSN-aware Runtime Adaptation)—a collection of a novel flow-control protocol (PAF) and an adaptive routing algorithm (PAR), to mitigate PSN in NoCs. Our best scheme achieves 14% and 12% improvements in the regional peak PSN and energy ef- ficiency, with an average of 4.6% performance overhead and marginal area and power footprints. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30		End of session Coffee Break in Exhibition Area

Time

Label

Presentation Title
Authors

14:00

11.2.1

CROSS-LAYER FLOORPLAN OPTIMIZATION FOR SILICON PHOTONIC NOCS IN MANY-CORE SYSTEMS
Speaker:
Ayse Coskun, Boston University, US
Authors:
Ayse Coskun¹, Anjun Gu², Warren Jin³, Ajay Jayant Joshi¹, Andrew B. Kahng², Jonathan Klamkin³, Yenai Ma¹, John Recchio², Vaishnav Srinivas² and Tiansheng Zhang¹
¹Boston University, US; ²University of California, San Diego, US; ³UC Santa Barbara, US
Abstract
Many-core chip architectures are now feasible, but the power consumption of electrical networks-on-chip does not scale well. Silicon photonic NoCs (PNoCs) are more scalable and power efficient, but floorplan optimization is challenging. Prior work optimizes PNoC floorplans through simultaneous place and route, but does not address cross-layer effects that span optical and electrical boundaries, chip thermal profiles, or effects of job scheduling policies. This paper proposes a more comprehensive, cross-layer optimization of the silicon PNoC and core cluster floorplan. Our simultaneous placement (locations of router groups and core clusters) and routing (waveguide layout) considers scheduling policy, thermal tuning, and heterogeneity in chip power profiles. The core of our optimizer is a mixed-integer linear programming formulation that minimizes NoC power, including (1) laser source power due to propagation, bend and crossing losses; (2) electrical and electrical-optical-electrical conversion power; and (3) thermal tuning power. Our experiments vary numbers of cores, optical data rate per wavelength, number of waveguides and other parameters to investigate scalability and tradeoffs through a large design space. We demonstrate how the optimal floorplan changes with cross-layer awareness: metrics of interest such as optimal waveguide length or thermal tuning power change significantly (up to 4X) based on power and utilization levels of cores, chip and cluster aspect ratio, and laser source sharing mechanism. Exploration of a large solution space is achieved with reasonable runtimes, and is perfectly parallelizable. Our optimizer thus affords designers with more accurate, cross-layer chip planning decision support to accelerate adoption of PNoC-based solutions.
Download Paper (PDF; Only available from the DATE venue WiFi)

14:30

11.2.2

ADAPTIVE MULTI-VOLTAGE SCALING IN WIRELESS NOC FOR HIGH PERFORMANCE LOW POWER APPLICATIONS
Speaker:
Sujay Deb, IIIT Delhi, IN
Authors:
Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore and Sujay Deb, IIIT Delhi, IN
Abstract
Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi hop long distance communication bottlenecks and opens up innumerable possibilities of topological innovations that are not possible otherwise. However, energy consumption in routers along with Wireless Interface (WI) components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure (routers, links, WIs). The usage of the routers and WIs are application dependent and for most cases performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable systems that can switch between both high performance and low power modes can cater to wide range of applications. In this paper, we propose a novel design methodology for energy efficient WNoC using Adaptive Multi-voltage Scaling (AMS) that reduces dynamic power consumption, along with power gating to prevent static power dissipation in routers and WIs. We evaluate our proposed design in presence of real and synthetic traffic patterns. This approach saves up to 62.50% of static power with less than 1% area overhead. In different traffic scenarios, the proposed WNoC reduces overall packet energy dissipation by 35% on average compared to a regular WNoC, without significant performance degradation. Design considerations for augmenting existing WNoCs with these routers and corresponding overheads are also presented.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:00

11.2.3

ENERGY EFFICIENT TRANSCEIVER IN WIRELESS NETWORK ON CHIP ARCHITECTURES
Speaker:
Davide Patti, University of Catania, IT
Authors:
Vincenzo Catania¹, Andrea Mineo¹, Salvatore Monteleone¹, Maurizio Palesi² and Davide Patti¹
¹University of Catania, IT; ²Kore University, IT
Abstract
The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs, account for a significant fraction of the total communication energy budget. In this paper, we propose a novel energy management scheme aimed at improving the energy efficiency of a WiNoC architecture based on the selective disabling of the power hungry modules that are predicted being not used during the forthcoming clock cycles.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

IP5-9, 115

PRADA: COMBATING VOLTAGE NOISE IN THE NOC POWER SUPPLY THROUGH FLOW-CONTROL AND ROUTING ALGORITHMS
Speaker:
Prabal Basu, Utah State University, US
Authors:
Prabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty and Sanghamitra Roy, Utah State University, US
Abstract
Network-on-Chip (NoC) has become the de-facto standard for on-chip communication in MPSoCs. The growing NoC power footprint, increase in the transistor current, and high switching speed of the logic devices, exacerbate the peak power supply noise (PSN) in the NoC power delivery network (PDN). Hence, preserving power supply integrity in the NoC PDN is critical. In this work, we propose PRADA (PSN-aware Runtime Adaptation)—a collection of a novel flow-control protocol (PAF) and an adaptive routing algorithm (PAR), to mitigate PSN in NoCs. Our best scheme achieves 14% and 12% improvements in the regional peak PSN and energy ef- ficiency, with an average of 4.6% performance overhead and marginal area and power footprints.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

End of session
Coffee Break in Exhibition Area

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