Date: Thursday 17 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 5

Chair:
Mohamed Sabry Aly, Stanford University, US

Co-Chair:
Semeen Rehman, Technische Universität Dresden, DE

This session explores several approaches for the analysis, simulation, and repair of integrated systems, from 3D ICs, to STT-RAMs.

Time	Label	Presentation Title Authors
11:00	10.7.1	(Best Paper Award Candidate) A HOLISTIC TRI-REGION MLC STT-RAM DESIGN WITH COMBINED PERFORMANCE, ENERGY, AND RELIABILITY OPTIMIZATIONS Speaker: Yiran Chen, University of Pittsburgh, US Authors: Wujie Wen1, Mengjie Mao2, Hai Li2, Yiran Chen2, Yukui Pei3 and Ning Ge3 1Florida International University, US; 2University of Pittsburgh, US; 3Tsinghua University, CN Abstract Multi-level cell spin-transfer torque random access memory (MLC STT-RAM) demonstrates great potentials in on chip cache design for its high storage density and non-volatility but also suffers from the degraded access time, reliability and energy efficiency. The existing MLC STT-RAM cache designs primarily focus on the performance and energy optimizations, however, often ignore the crucial demand for reliability. In this work, we propose a tri-region MLC STT-RAM cache design (TMSC) to simultaneously meet the requirements of performance, energy, and reliability. The tri-region MLC STT-RAM cache is optimized partitioned into fast, mixed, and slow ways according to different access performance, energy and reliability. A new error correction code (ECC) scheme, namely, non-uniform strength ECC (NUS-ECC), is also developed to tolerate the different bit failure rates in these ways. Compared to the latest performance-driven MLC STT-RAM cache design with pessimistic ECC scheme, our TMSC technique can improve the system performance and energy by averagely 9.3% and 9.4%, respectively, for various applications. The additional area cost associated with NUS-ECC is limited by 3.2% compared to the pessimistic ECC scheme. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	10.7.2	THERMAL-AWARE TSV REPAIR FOR ELECTROMIGRATION IN 3D ICS Speaker: Shengcheng Wang, Karlsruhe Institute of Technology (KIT), DE Authors: Shengcheng Wang1, Krishnendu Chakrabarty2 and Mehdi Tahoori1 1Karlsruhe Institute of Technology (KIT), DE; 2Duke University, US Abstract Electromigration (EM) occurrence on through-silicon-vias (TSVs) is a major reliability concern for Three-Dimensional Integrated-Circuits (3D ICs), and EM can severely reduce the mean-time-to-failure (MTTF). In this work, a novel fault tolerant technique is proposed to increase the MTTF of the functional TSV network through the assignment of spare TSVs to EM-vulnerable functional TSVs. The objective is to meet the target MTTF with minimum spare TSVs and minimal impact on the circuit timing. By considering the impact of temperature variation, the proposed technique provides a more robust repair solution for EM-induced TSV defects with minimum delay overhead, compared to previous thermal-unaware methods. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	10.7.3	ELECTROTHERMAL SIMULATION OF BONDING WIRE DEGRADATION UNDER UNCERTAIN GEOMETRIES Speaker: Thorben Casper, Technische Universität Darmstadt, DE Authors: Thorben Casper1, Herbert De Gersem1, Renaud Gillon2, Tomas Gotthans3, Tomáš Kratochvíl3, Peter Meuris4 and Sebastian Schöps1 1Technische Universität Darmstadt, DE; 2ON Semiconductor, BE; 3Brno University of Technology, CZ; 4Magwel NV, Leuven, BE Abstract In this paper, electrothermal field phenomena in electronic components are considered. This coupling is tackled by multiphysical field simulations using the Finite Integration Technique (FIT). In particular, the design of bonding wires with respect to thermal degradation is investigated. Instead of resolving the wires by the computational grid, lumped element representations are introduced as point-to-point connections in the spatially distributed model. Fabrication tolerances lead to uncertainties of the wires' parameters and influence the operation and reliability of the final product. Based on geometric measurements, the resulting variability of the wire temperatures is determined using the stochastic electrothermal field-circuit model. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	IP5-8, 250	SAMPLING-BASED BUFFER INSERTION FOR POST-SILICON YIELD IMPROVEMENT UNDER PROCESS VARIABILITY Speaker: Grace Li Zhang, Technische Universität München (TUM), DE Authors: Grace Li Zhang, Bing Li and Ulf Schlichtmann, Technische Universität München (TUM), DE Abstract At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning buffers can be inserted into circuits to balance timing budgets of critical paths with their neighbors. After manufacturing, these clock buffers can be configured for each chip individually so that chips with timing failures may be rescued to improve yield. In this paper, we propose a sampling-based method to determine the proper locations of these buffers. The goal of this buffer insertion is to reduce the number of buffers and their ranges, while still maintaining a good yield improvement. Experimental results demonstrate that our algorithm can achieve a significant yield improvement (up to 35%) with only a small number of buffers. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 13:30 - 14:00