Date: Tuesday 25 March 2014
Time: 17:30 - 19:30
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB04.01	QUANTUMEDA: A VISUALIZATION AND DESIGN ENVIRONMENT FOR TOPOLOGICAL QUANTUM CIRCUITS Authors: Ilia Polian, Wolfgang Wallner and Alexandru Paler, University of Passau, DE Abstract Quantum circuits use quantum-mechanical properties of certain physical systems, such as superposition and entanglement, to perform massively parallel calculations. They provide polynomial algorithms for problems for which only inefficient algorithms with asymptotically-exponential running time are known in conventional mod-els of computation. Building a scalable quantum computer that can process a large number of quantum bits (qubits) is one of the grand challenges of modern science. While first small quantum computers have been experimentally demonstrated and a number of implementation technologies have been suggested, all of them encounter difficulties when it comes to scaling. The central difficulty is the high susceptibility of such circuits to noise and decoherence, which necessitates the use of special quantum error correction. Topological quantum computing (TQC) is a paradigm that offers a path to scalability. It strikes a balance between systematic, intuitive methods to design large computations, and relatively loose requirements on the vulnerability of individual qubits to errors. The availability of a platform for implementing large quantum algo-rithm constitutes the need for methods to manage design complexity, including automatic synthesis, optimiza-tion, compaction, verification and visualization of TQC circuits. Topological quantum circuits are based on a three-dimensional cluster of qubits which supports highly efficient topological quantum error-correcting codes. In this way, the circuits can operate even though its individual qubits are subject to relatively high error rates. We will present the first environment for design of TQC circuits. The environment allows the user to graphically enter the structure of a circuit, add, delete and re-shape individual qubits, and perform optimization and compaction (both manually and by global replacement). The circuits are represented on an intermediate technology-independent level, where "logical qubits" that consist of a large number of physical qubits perform error-corrected operations. For example, the circuit in Fig. 1 shows an error-corrected CNOT gate implemented by four logical qubits represented by colored structures. The optimized representation can be translated into instruction sequences for a classical computer that operates the actual quantum hardware. More information ...
UB04.02	AIDA: ANALOG IC DESIGN AUTOMATION Authors: Nuno Horta1, Nuno Lourenço2, Ricardo Martins2, Ricardo Póvoa2, António Canelas2 and Pedro Ventura1 1Instituto de Telecomunicacoes, PT; 2Instituto de Telecomunicacoes / Instituto Superior Técnico, PT Abstract This demonstration presents AIDA, an analog integrated circuit (IC) design automation environment. AIDA includes two main modules, namely, AIDA-C and AIDA-L. AIDA-C is a circuit-level synthesis tool which uses state-of-the-art multi-objective multi-constrained optimization kernels, based on evolutionary computation techniques, where the robustness of the solutions is attained by considering a layout-aware approach and, also, extreme process variations by means of PVT corner analysis. The circuit's performance is measured using Spectre®, ELDO® or HSPICE® electrical simulators as evaluation engines. AIDA-L considers the device sizes and the best floorplan, obtained with AIDA-C, and generates the complete layout by placing and routing the devices, while fulfilling the technology design rules by using built-in design-rule check (DRC) and layout-versus-schematic (LVS) procedures. In order to demonstrate AIDA design environment several analog circuit structures, e.g., OTAs, LNAs, LC-Oscillators, etc., will be synthesized in a 130nm CMOS technology. AIDA-C is demonstrated for circuit-level sizing and optimization by generating a family of Pareto Optimal solutions based on user performance and functional specifications. AIDA-L is demonstrated by generating the layout of a user selected solution from AIDA-C, taking into account electrical currents information to mitigate electromigration and IR-drop effects, and also wiring symmetry for multiport multi-terminal signal nets of analog ICs. More information ...
UB04.03	PATN: A PERFORMANCE ANALYSIS TOOL FOR NOC Authors: Yang Chen and Zhonghai Lu, KTH Royal Institute of Technology, SE Abstract With processors increased onto a single chip, and more and more time sensitive applications added to on-chip systems, performance bound analysis becomes essential for QoS Network-on-Chip (NoC) designs and evaluations. For the purpose of providing the reliable and automated analysis for QoS NoC, we propose PATN (Performance Analysis Tool for NoC), which automatically computes the end-to-end delay bounds of data flows, and backlog bounds of buffers for NoC with arbitrary topology. PATN is designed based on network calculus, which lies on solid mathematical foundations and provides well-guaranteed accuracy of the results. Network Calculus based analysis has been successfully employed for various communications networks, such as SpaceWire, AFDX, etc.. For example, Airbus adopted and approved the network calculus based analysis for certification on its aircraft A380. In this demonstration, we give a whole view of PATN through two segments. First, we explain the architecture and main functions; show the working flow and printing log by analysing end-to-end delay bound of a data flow in a simple network. The log shows that the analysis follows the theoretical methodology exactly, hence to obtain the correct and tight results, which as good as that the theory can achieve. Second, we use PATN to analyse the delay bounds and backlog bounds for 3 NoCs with different topologies -- binary tree, mesh, and hierarchical topology of binary tree and mesh. The analyses demonstrate computation speed and scalability of PATN. Moreover, comparisons of the delay bound, computed with different configuration parameters of the flows and routers, are conducted. It shows how the delay bound is effected by the parameters. More information ...
UB04.04	GEMINI: A NEW SYNTHESIS AND OPTIMIZATION TOOL FOR GRAPHENE-BASED DIGITAL DEVICES Authors: Valerio Tenace, Andrea Calimera, Massimo Poncino and Enrico Macii, Politecnico di Torino, IT Abstract Gemini is a synthesis and optimization software for graphene-based digital devices. Given a combinational circuit description through its boolean representation, Gemini produces a SPICE netlist mapped with graphene PN-Junction gates. The software is composed of a parser library to handle input circuit descriptions, a characterization library of graphene gates used in the synthesis process, a Biconditional Binary Decision Diagram library used to manipulate logic networks in Pass-XNOR logic in order to better exploit the intrinsic characteristics of the adopted graphene gates, and a number of optimization algorithms designed to produce better results in terms of area and thus power consumption. As a stand-alone software or as a library easy to integrate into state-of-the-art tools, Gemini represents a first step of an enabling technology for future synthesis and optimization processes for graphene-based devices. More information ...
UB04.05	HWDEBLUR: DESIGN OF A HIGH PERFORMANCE CORE FOR REMOVING BLUR EFFECT ON IMAGES Authors: Giuseppe Airo' Farulla, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo and Pascal Trotta, Politecnico di Torino, IT Abstract This work aims at developing a high performance FPGA-based IP-core able to perform a deblurring algorithm in real-time. Modern approaches to deblurring usually either only handle simple types of blur, or need heavy user inter-action. Moreover, they usually require several minutes (or even whole hours) to process a single image. Our purpose is to study the current state-of-the-art and identify the best deblurring algorithms that are suitable for a hardware implementation. The selected algorithm is optimized and implemented in hardware in order to perform the deblurring task with highest possible performances. More information ...
UB04.06	ENERGY-MODULATED COMPUTING Authors: Maxim Rykunov, Reza Ramezani, Abdullah Baz, Xuefu Zhang, Delong Shang, Andrey Mokhov, Danil Sokolov, Fei Xia and Alex Yakovlev, Newcastle University, GB Abstract This demo will illustrate the principle of energy-modulated computing according to which the flow of energy entering a computing system determines its computational flow. This principle will be fundamental for building future autonomous systems, such as those powered by energy harvesting sources and aimed for survival in power-deficient conditions. The demo includes a set of experimental circuits (with three VLSI chips and PCBs) to work in variable power supply conditions and software tools for digital and analogue co-design (Workcraft, Petrify, MPSAT). More information ...
UB04.07	ID.FIX: AN EDA TOOL FOR FIXED-POINT REFINEMENT OF EMBEDDED SYSTEMS Authors: Olivier Sentieys1, Daniel Menard2 and Nicolas Simon3 1INRIA, FR; 2INSA Rennes, FR; 3University of Rennes, FR Abstract Most of digital image and signal processing algorithms are implemented into architectures based on fixed-point arithmetic to satisfy the cost and power consumption constraints of embedded systems. The fixed-point conversion process (or refinement) is crucial for reducing the time-to-market. Design tools to automate this phase and to explore the design space are thus required. The ID.Fix EDA tool based on the compiler infrastructure GECOS allows for the convertion of a floating-point C source code into a C code using fixed-point data types. The data word-lengths are optimized by minimizing the implementation cost under accuracy constraint. To obtain low optimization time, an analytical approach is used to evaluate the fixed-point computation accuracy. This approach is valid for systems made-up of any (smooth) arithmetic operations. More information ...
UB04.09	FAULTIFY: PROBABILISTIC CIRCUIT FAULT EMULATION Authors: David May and Walter Stechele, TUM, DE Abstract We want to demonstrate an FPGA-based probability-aware fault emulator and its corresponding algorithms in the context of a real-time H.264 decoder. The demo will show that reliability constraints can be relaxed inside the circuit without noticeable degradation of the image quality when carefully investigating where the constraints can be relaxed. We will show how this investigation can to be done using our emulator and we will show the effect of a relaxed robustness of the circuit in real-time. More information ...
19:30	End of session