Date: Tuesday 25 March 2014
Time: 12:30 - 15:00
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB02.01	QUANTUMEDA: A VISUALIZATION AND DESIGN ENVIRONMENT FOR TOPOLOGICAL QUANTUM CIRCUITS Authors: Ilia Polian, Wolfgang Wallner and Alexandru Paler, University of Passau, DE Abstract Quantum circuits use quantum-mechanical properties of certain physical systems, such as superposition and entanglement, to perform massively parallel calculations. They provide polynomial algorithms for problems for which only inefficient algorithms with asymptotically-exponential running time are known in conventional mod-els of computation. Building a scalable quantum computer that can process a large number of quantum bits (qubits) is one of the grand challenges of modern science. While first small quantum computers have been experimentally demonstrated and a number of implementation technologies have been suggested, all of them encounter difficulties when it comes to scaling. The central difficulty is the high susceptibility of such circuits to noise and decoherence, which necessitates the use of special quantum error correction. Topological quantum computing (TQC) is a paradigm that offers a path to scalability. It strikes a balance between systematic, intuitive methods to design large computations, and relatively loose requirements on the vulnerability of individual qubits to errors. The availability of a platform for implementing large quantum algo-rithm constitutes the need for methods to manage design complexity, including automatic synthesis, optimiza-tion, compaction, verification and visualization of TQC circuits. Topological quantum circuits are based on a three-dimensional cluster of qubits which supports highly efficient topological quantum error-correcting codes. In this way, the circuits can operate even though its individual qubits are subject to relatively high error rates. We will present the first environment for design of TQC circuits. The environment allows the user to graphically enter the structure of a circuit, add, delete and re-shape individual qubits, and perform optimization and compaction (both manually and by global replacement). The circuits are represented on an intermediate technology-independent level, where "logical qubits" that consist of a large number of physical qubits perform error-corrected operations. For example, the circuit in Fig. 1 shows an error-corrected CNOT gate implemented by four logical qubits represented by colored structures. The optimized representation can be translated into instruction sequences for a classical computer that operates the actual quantum hardware. More information ...
UB02.02	AN AUTOMATED DESIGN FLOW FOR FAST PROTOTYPING OF SIMULINK MODELS ONTO MPSOC Authors: Francesco Robino and Johnny Öberg, Royal Institute of Technology, SE Abstract Simulink is a modelling environment suitable to model embedded systems at system-level. However there is no standard to rapidly prototype Simulink models onto modern multiprocessor system-on-chip (MPSoC). In this demonstration we show how our NoC System Generator tool can be used as part of an automated platform-based design flow to synthesize a Simulink model to a network-on-chip based MPSoC implementation on FPGA. The performance of the generated prototype scales with the number of processors. More information ...
UB02.03	CUCUMBER-VERILOG: BEHAVIOR DRIVEN DEVELOPMENT FOR CIRCUIT DESIGN AND VERIFICATION Authors: Melanie Diepenbeck, Mathias Soeken, Ulrich Kühne and Rolf Drechsler, University of Bremen, DE Abstract When designing hardware one usually applies a top-down approach in which starting from a natural language specification a design is implemented and afterwards tested and verified for correctness. In contrast, software development is pushed towards agile techniques such as Test Driven Development (TDD), where tests play a central role in driving the implementation. Behavior Driven Development (BDD) extends TDD by using natural language style scenarios to describe the tests. Essentially, in both techniques testing and implementation is interleaved: first, test cases are written, and secondly, the implementation is extended to satisfy them. Since nowadays 70% of the the effort to design hardware systems is spent on verification, test and verification should receive more attention and be applied as soon as possible. We present a BDD tool tailored for the Verilog hardware description language which enables a new design flow for hardware design, test, and verification. BDD acceptence tests are readily given by means of the natural language specification. Assigning test code to their sentences yields a testbench which serves as a starting point for the implementation. In the same time, the natural language scenarios form a test documentation that is easily accessable also to non-experts. Furthermore, our tool allows for the generalization of test cases to properties suitable for formal verification. As properties are typically more difficult to formalize than test cases, our approach facilitates the access to formal verification. In our demonstration, we will show how to implement hardware designs using our BDD tool and how properties are generalized from test cases which can then can be verified by a model checker automatically. More information ...
UB02.04	BUILDING A PROTOTYPING PLATFORM FOR INVESTIGATING THE IMPACT OF ATTACKS AGAINST AUTOMOTIVE NETWORKS Authors: Alexander Stühring1, Günter Ehmen1 and Sibylle Fröschle2 1University of Oldenburg, DE; 2OFFIS, DE Abstract The University of Oldenburg is working on solutions to ensure a secure communication in the automotive domain. This is a key requirement for safe applications in the context of future Car2X applications. In order to achieve this goal we are using a self-developed prototyping platform to analyze and demonstrate the impact of attacks on in-vehicle buses and wireless networks. Moreover, the visitors are able to start attacks and observe the consequences in a simulated driving scenario. More information ...
UB02.05	HWDEBLUR: DESIGN OF A HIGH PERFORMANCE CORE FOR REMOVING BLUR EFFECT ON IMAGES Authors: Giuseppe Airo' Farulla, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo and Pascal Trotta, Politecnico di Torino, IT Abstract This work aims at developing a high performance FPGA-based IP-core able to perform a deblurring algorithm in real-time. Modern approaches to deblurring usually either only handle simple types of blur, or need heavy user inter-action. Moreover, they usually require several minutes (or even whole hours) to process a single image. Our purpose is to study the current state-of-the-art and identify the best deblurring algorithms that are suitable for a hardware implementation. The selected algorithm is optimized and implemented in hardware in order to perform the deblurring task with highest possible performances. More information ...
UB02.06	ENERGY-MODULATED COMPUTING Authors: Maxim Rykunov, Reza Ramezani, Abdullah Baz, Xuefu Zhang, Delong Shang, Andrey Mokhov, Danil Sokolov, Fei Xia and Alex Yakovlev, Newcastle University, GB Abstract This demo will illustrate the principle of energy-modulated computing according to which the flow of energy entering a computing system determines its computational flow. This principle will be fundamental for building future autonomous systems, such as those powered by energy harvesting sources and aimed for survival in power-deficient conditions. The demo includes a set of experimental circuits (with three VLSI chips and PCBs) to work in variable power supply conditions and software tools for digital and analogue co-design (Workcraft, Petrify, MPSAT). More information ...
UB02.07	ID.FIX: AN EDA TOOL FOR FIXED-POINT REFINEMENT OF EMBEDDED SYSTEMS Authors: Olivier Sentieys1, Daniel Menard2 and Nicolas Simon3 1INRIA, FR; 2INSA Rennes, FR; 3University of Rennes, FR Abstract Most of digital image and signal processing algorithms are implemented into architectures based on fixed-point arithmetic to satisfy the cost and power consumption constraints of embedded systems. The fixed-point conversion process (or refinement) is crucial for reducing the time-to-market. Design tools to automate this phase and to explore the design space are thus required. The ID.Fix EDA tool based on the compiler infrastructure GECOS allows for the convertion of a floating-point C source code into a C code using fixed-point data types. The data word-lengths are optimized by minimizing the implementation cost under accuracy constraint. To obtain low optimization time, an analytical approach is used to evaluate the fixed-point computation accuracy. This approach is valid for systems made-up of any (smooth) arithmetic operations. More information ...
UB02.08	MICROTESK: RECONFIGURABLE OPEN-SOURCE FRAMEWORK FOR TEST PROGRAM GENERATION Authors: Andrei Tatarnikov, Alexander Kamkin and Artem Kotsynyak, Institute for System Programming of the Russian Academy of Sciences (ISP RAS), RU Abstract Test program generation plays a major role in functional verification of microprocessors. Due to tremendous growth in complexity of modern designs and rigid constraints on time to market, it becomes an increasingly difficult task. In spite of powerful test program generation tools available in the market, development of functional tests is still known to be the bottleneck of the microprocessor design cycle. The common problem is that it takes a significant effort to reconfigure a test program generation environment for a new microprocessor design. The model-based approach applied in the state-of-the-art tools, like Genesys-Pro (IBM Research), still does not provide enough flexibility since creating a microprocessor model is difficult and requires special knowledge and skills. MicroTESK, the open-source test program generation framework being developed at ISPRAS, offers an approach to ease customization by using light-weight formal specifications to describe the target microprocessor architecture. The approach helps reduce the effort needed to create a microprocessor model and, consequently, minimize the time required to create functional tests. In addition to gaining flexibility, the use of formal specifications also allows automated extraction of knowledge about test situations that occur in a microprocessor (coverage model), thus, facilitating creating directed tests and improving test coverage. By the present moment, a demo prototype of MicroTESK has been implemented. It uses the Sim-nML architecture description language to specify the target microprocessor architecture and provides a convenient Ruby-based language for creating test templates that serve as an abstract description of test programs to be generated. The current version of the framework focuses primarily on RISK microprocessors including ARM, MIPS and SPARK. Supported test generation methods include random, combinatorial, template-based and model-based generation. Flexible architecture of the framework allows adding support for new test generation methods. More information ...
UB02.09	FAULTIFY: PROBABILISTIC CIRCUIT FAULT EMULATION Authors: David May and Walter Stechele, TUM, DE Abstract We want to demonstrate an FPGA-based probability-aware fault emulator and its corresponding algorithms in the context of a real-time H.264 decoder. The demo will show that reliability constraints can be relaxed inside the circuit without noticeable degradation of the image quality when carefully investigating where the constraints can be relaxed. We will show how this investigation can to be done using our emulator and we will show the effect of a relaxed robustness of the circuit in real-time. More information ...
15:00	End of session
16:00	Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).