- DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)
-
Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.
The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.
DATE 2021 Early Author Notification
The accepted papers at DATE 2021 are listed below. Detailed information follow in the next days
Paper ID | Paper Title | Status |
---|---|---|
1003 | RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification | Interactive Presentation (IP) |
1005 | Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator | Interactive Presentation (IP) |
1006 | Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA | Regular Presentation |
1010 | MARVEL: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D | Regular Presentation |
1011 | Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies | Regular Presentation |
1017 | Fan-out of 2 Triangle Shape Spin Wave Logic Gates | Regular Presentation |
1022 | A GPU-enabled Level-Set Method for Mask Optimization | Interactive Presentation (IP) |
1023 | SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching | Interactive Presentation (IP) |
1032 | An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks | Regular Presentation |
1033 | Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays | Interactive Presentation (IP) |
1034 | An Event-Driven System-Level Noise Analysis Methodology for RF Systems | Regular Presentation |
1038 | HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms | Interactive Presentation (IP) |
1040 | Characterizing and Optimizing EDA Flows for the Cloud | Interactive Presentation (IP) |
1041 | Training Deep Neural Networks in 8-Bit Fixed Point with Dynamic Shared Exponent Management | Regular Presentation |
1042 | SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture | Regular Presentation |
1043 | Approximate Computation of Post-synaptic Spikes Reduces Bandwidth to Synaptic Storage in a Model of Cortex | Interactive Presentation (IP) |
1044 | Improving the Energy Efficiency of STT-MRAM Based Approximate Cache | Regular Presentation |
1045 | Digital Test of ZigBee Transmitters: Validation in Industrial Test Environment | Regular Presentation |
1047 | Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks | Regular Presentation |
1048 | Enhancements of Model and Method in Lithography Hotspot Identification | Regular Presentation |
1054 | Tiny-CFA: A Minimalistic Approach for Control Flow Attestation Using Verified Proofs of Execution | Regular Presentation |
1055 | SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators | Regular Presentation |
1056 | RTL Design Framework for Embedded Processor by Using C++ Description | Interactive Presentation (IP) |
1057 | O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands | Regular Presentation |
1059 | Receptive-Field and Switch-Matrices Based ReRAM Accelerator with Low Digital-Analog Conversion for CNNs | Interactive Presentation (IP) |
1065 | Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM | Regular Presentation |
1066 | HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators | Regular Presentation |
1077 | A Framework for Efficient and Binary Clustering in High-Dimensional Space | Regular Presentation |
1078 | OnlineHD: Robust, Efficient, and Single-Pass Online Learning Using Hyperdimensional System | Regular Presentation |
1079 | Data-Driven Electrostatics Analysis Based on Physics-Constrained Deep Learning | Regular Presentation |
1080 | Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols | Regular Presentation |
1081 | TruLook: A Framework for Configurable GPU Approximation | Interactive Presentation (IP) |
1087 | TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation | Regular Presentation |
1094 | FPGA Architectures for Approximate Dense SLAM Computing | Regular Presentation |
1095 | Post Silicon Validation of the MMU | Regular Presentation |
1098 | ICP and IC3 | Regular Presentation |
1100 | Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling | Regular Presentation |
1103 | Thermal-Aware Design and Management of Embedded Real-Time Systems | Interactive Presentation (IP) |
1112 | Feeding Three Birds with One Scone: A Generic Duplication Based Countermeasure to Fault Attacks | Interactive Presentation (IP) |
1118 | A Runtime Reconfigurable Design of Compute-in-Memory Based Hardware Accelerator | Regular Presentation |
1122 | Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks | Regular Presentation |
1124 | Verifying the Conformance of a Driver Implementation to the VirtIO Specification | Regular Presentation |
1127 | Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem | Regular Presentation |
1129 | A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices | Regular Presentation |
1132 | Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing | Regular Presentation |
1137 | A Learning-Based Methodology for Accelerating Cell-Aware Model Generation | Regular Presentation |
1142 | Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization | Regular Presentation |
1153 | Watermarking of Behavioral IPs: A Practical Approach | Regular Presentation |
1155 | Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions | Interactive Presentation (IP) |
1163 | MG-DmDSE: Multi-Granularity Domain Design Space Exploration Considering Function Similarity | Regular Presentation |
1167 | An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays | Regular Presentation |
1168 | Joint Sparsity with Mixed Granularity for Efficient GPU Implementation | Interactive Presentation (IP) |
1169 | LAP: A Lightweight Automata Processor for Pattern Matching Tasks | Regular Presentation |
1173 | Autosymmetry of Incompletely Specified Functions | Regular Presentation |
1177 | TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications | Regular Presentation |
1178 | An On-chip Layer-wise Training Method for RRAM Based Computing-in-memory Chips | Interactive Presentation (IP) |
1182 | Blender: A Traffic-Aware Container Placement for Containerized Data Centers | Interactive Presentation (IP) |
1188 | COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter | Regular Presentation |
1191 | Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes | Regular Presentation |
1193 | Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis | Interactive Presentation (IP) |
1196 | Morphable Convolutional Neural Network for Biomedical Image Segmentation | Interactive Presentation (IP) |
1199 | Speeding up MUX-FSM Based Stochastic Computing for On-device Neural Networks | Interactive Presentation (IP) |
1201 | Leveraging Processor Modeling and Verification for General Hardware Modules | Regular Presentation |
1204 | PATRON: A Pragmatic Approach for Encoding Laser Fault Injection Resistant FSMs | Regular Presentation |
1207 | Value Similarity Extensions for Approximate Computing in General-Purpose Processors | Regular Presentation |
1209 | PiPoMonitor: Mitigating Cross-core Cache Attacks Using the Auto-Cuckoo Filter | Regular Presentation |
1210 | SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging | Regular Presentation |
1215 | Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design | Regular Presentation |
1226 | A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing | Regular Presentation |
1232 | HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search | Interactive Presentation (IP) |
1249 | An Efficient Programming Framework for Memristor-based Neuromorphic Computing | Regular Presentation |
1252 | Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory | Interactive Presentation (IP) |
1254 | Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture | Regular Presentation |
1255 | Workload- and User-aware Battery Lifetime Management for Mobile SoCs | Regular Presentation |
1262 | ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification | Interactive Presentation (IP) |
1268 | Scalar Replacement in the Presence of Multiple Write Accesses for Accelerator Design with High-level Synthesis | Regular Presentation |
1271 | Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design | Regular Presentation |
1273 | Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning | Regular Presentation |
1278 | Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints | Regular Presentation |
1279 | A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing | Regular Presentation |
1283 | NoC Performance Model for Efficient Network Latency Estimation | Regular Presentation |
1285 | In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories | Regular Presentation |
1287 | Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters | Regular Presentation |
1290 | Global Placement with Deep Learning-Enabled Explicit Routability Optimization | Interactive Presentation (IP) |
1291 | vProfile: Voltage-Based Anomaly Detection in Controller Area Networks | Regular Presentation |
1295 | HyDREA: Towards More Robust and Efficient Machine Learning Systems with Hyperdimensional Computing | Regular Presentation |
1297 | Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices | Regular Presentation |
1301 | SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays | Regular Presentation |
1302 | GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking | Regular Presentation |
1304 | Towards Non-intrusive Malware Detection for Industrial Control Systems | Interactive Presentation (IP) |
1307 | Modeling and Analysis for Energy-Driven Computing Using Statistical Model-Checking | Regular Presentation |
1319 | A FeRAM Based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training | Regular Presentation |
1324 | A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications | Regular Presentation |
1327 | Efficient Identification of Critical Faults in Memristor Crossbars for Deep Neural Networks | Interactive Presentation (IP) |
1328 | Block Attribute-aware Data Reallocation to Alleviate Read Disturb in SSDs | Interactive Presentation (IP) |
1329 | Sequential Logic Encryption against Model Checking Attack | Interactive Presentation (IP) |
1332 | Efficient Hardware-assisted Out-place Update for Persistent Memory | Regular Presentation |
1333 | SC4MEC: Automated Implementation of a Secure Hierarchical Calculus for Mobile Edge Computing | Interactive Presentation (IP) |
1334 | Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing | Regular Presentation |
1336 | LSP: Collective Cross-Page Prefetching for NVM | Regular Presentation |
1342 | Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building | Interactive Presentation (IP) |
1348 | Making Obfuscated PUFs Secure against Power Side-Channel Based Modeling Attacks | Regular Presentation |
1351 | Reliability-Driven Neuromorphic Computing Systems Design | Regular Presentation |
1352 | OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy | Interactive Presentation (IP) |
1353 | A Quantization Framework for Neural Network Adaption at the Edge | Regular Presentation |
1354 | Technology Lookup Table Based Default Timing Assertions for Hierarchical Timing Closure | Regular Presentation |
1355 | ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks | Regular Presentation |
1358 | Runtime Fault Injection Detection for FPGA-based DNN Execution Using Siamese Path Verification | Interactive Presentation (IP) |
1361 | SealPK: Sealable Protection Keys for RISC-V | Interactive Presentation (IP) |
1369 | Neighbor Oblivious Learning(NObLe) for Device Localization and Tracking | Interactive Presentation (IP) |
1376 | Intermittent Computing with Efficient State Backup by Asynchronous DMA | Regular Presentation |
1378 | Surviving Transient Power Failures with SRAM Data Retention | Regular Presentation |
1379 | Virtual Gang Scheduling of Parallel Real-Time Tasks | Regular Presentation |
1380 | Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks | Regular Presentation |
1381 | ManiHD: Efficient Hyper-Dimensional Learning Using Manifold Trainable Encoder | Regular Presentation |
1386 | GOMIL: Global Optimization of Multiplier by Integer Linear Programming | Regular Presentation |
1387 | Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking | Interactive Presentation (IP) |
1389 | Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator | Regular Presentation |
1394 | Timing Debugging for Cyber-Physical Systems | Regular Presentation |
1396 | Fault-Criticality Assessment for AI Accelerators Using Graph Convolutional Networks | Interactive Presentation (IP) |
1397 | Modeling Silicon-Photonic Neural Networks under Uncertainties | Interactive Presentation (IP) |
1399 | Forseti: An Efficient Basic-block-level Sensitivity Analysis Framework towards Multi-bit Faults | Interactive Presentation (IP) |
1401 | Neuron Fault Tolerance in Spiking Neural Networks | Regular Presentation |
1404 | CHITIN: A Comprehensive In-thread InstructionReplication Technique against Transient Faults | Regular Presentation |
1413 | Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization | Regular Presentation |
1416 | Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup | Interactive Presentation (IP) |
1419 | A Case for Emerging Memories in DNN Accelerators | Interactive Presentation (IP) |
1421 | Compilation Flow for Classically Defined Quantum Operations | Interactive Presentation (IP) |
1426 | A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing | Regular Presentation |
1427 | RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery | Regular Presentation |
1428 | MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA | Regular Presentation |
1432 | Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence | Interactive Presentation (IP) |
1433 | FTApprox: A Fault-Tolerant Approximate Arithmetic Computing Data Format | Interactive Presentation (IP) |
1434 | Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs | Regular Presentation |
1436 | Exploring Deep Learning for In-Field Fault Detection in Microprocessors | Interactive Presentation (IP) |
1437 | Automatic Scalable System for the Coverage Directed Generation (CDG) Problem | Regular Presentation |
1444 | AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators | Regular Presentation |
1446 | Opportunistic IP Birthmarking Using Side Effects of Code Transformations on High-Level Synthesis | Interactive Presentation (IP) |
1447 | Estimation of Linux Kernel Execution Path Uncertainty for Safety Software Test Coverage | Regular Presentation |
1448 | Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks | Regular Presentation |
1449 | HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction | Regular Presentation |
1451 | M2H: Optimizing F2FS via Multi-log Delayed Writing and Modified Segment Cleaning Based on Dynamically Identified Hotness | Interactive Presentation (IP) |
1453 | Triple Fixed-Point MAC Unit for Deep Learning | Interactive Presentation (IP) |
1459 | As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation | Regular Presentation |
1462 | A Containerized ROS-compliant Verification Environment for Robotic Systems | Interactive Presentation (IP) |
1463 | FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays | Regular Presentation |
1470 | Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures | Regular Presentation |
1472 | Efficient Tensor Cores Support in TVM for Low-Latency Deep Learning | Interactive Presentation (IP) |
1475 | MDARTS: Multi-objective Differentiable Neural Architecture Search | Regular Presentation |
1476 | MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification | Interactive Presentation (IP) |
1478 | Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory | Regular Presentation |
1489 | A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition | Regular Presentation |
1491 | HOST: HLS Obfuscations against SMT ATtack | Regular Presentation |
1493 | Synthesis of SI Circuits from Burst-Mode Specifications | Interactive Presentation (IP) |
1494 | Blind Side-Channel SIFA | Regular Presentation |
1497 | Online Latency Monitoring of Time-sensitive Event Chains in Safety-critical Applications | Interactive Presentation (IP) |
1503 | Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies | Regular Presentation |
1504 | Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators | Regular Presentation |
1505 | NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks | Regular Presentation |
1507 | Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language Processing | Interactive Presentation (IP) |
1513 | Optimized Multi-Memristor Model Based Low Energy and Resilient Current-Mode Multiplier Design | Interactive Presentation (IP) |
1516 | TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems | Regular Presentation |
1520 | Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance | Regular Presentation |
1522 | Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture | Regular Presentation |
1523 | HTnet: Transfer Learning for Golden Chip-Free Hardware Trojan Detection | Regular Presentation |
1525 | Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs | Interactive Presentation (IP) |
1529 | Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks | Interactive Presentation (IP) |
1530 | Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips | Interactive Presentation (IP) |
1533 | Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation | Regular Presentation |
1534 | Towards a Firmware TPM on RISC-V | Interactive Presentation (IP) |
1535 | Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation | Regular Presentation |
1539 | Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips | Regular Presentation |
1540 | Library-free Structure Recognition for Analog Circuits | Regular Presentation |
1541 | Modeling, Implementation, and Analysis of XRCE-DDS Applications in Distributed Multi-processor Real-time Embedded Systems | Interactive Presentation (IP) |
1544 | Testing Resistive Memory Based Neuromorphic Architectures Using Reference Trimming | Interactive Presentation (IP) |
1558 | Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs | Regular Presentation |
1561 | Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques | Regular Presentation |
1565 | Reliability-Aware Quantization for Anti-Aging NPUs | Regular Presentation |
1567 | WISER: Deep Neural Network Weight-bit Inversion for State Error Reduction in MLC NAND Flash | Interactive Presentation (IP) |
1570 | Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks | Regular Presentation |
1579 | Stochastic Quantum Circuit Simulation Using Decision Diagrams | Regular Presentation |
1580 | Towards AQFP-Capable Physical Design Automation | Regular Presentation |
1584 | Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation | Interactive Presentation (IP) |
1590 | Generic Sample Preparation for Different Microfluidic Platforms | Interactive Presentation (IP) |
1592 | Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors | Regular Presentation |
1594 | Circuit Models for the Co-simulation of Superconducting Quantum Computing Systems | Regular Presentation |
1597 | PTierDB: Building Better Read-Write Cost Balanced Key-Value Stores for Small Data on SSD | Regular Presentation |
1609 | Side-channel Attack on Rainbow Post-quantum Signature | Interactive Presentation (IP) |
1610 | Grinch: A Cache Attack against GIFT Lightweight Cipher | Regular Presentation |
1624 | WavePro 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining | Regular Presentation |
1628 | Exploring Micro-architectural Side-channel Leakages through Statistical Testing | Interactive Presentation (IP) |
1643 | Towards Automatic Design and Verification for Level 3 of the European Train Control System | Regular Presentation |
1645 | A Low-cost BLE-based Distance Estimation, Occupancy Detection, and Counting System | Interactive Presentation (IP) |
1650 | A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing | Interactive Presentation (IP) |
1657 | BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter | Interactive Presentation (IP) |
1658 | FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node | Interactive Presentation (IP) |
1670 | Response Time Analysis of Lazy Round Robin | Regular Presentation |
1673 | Formulation of Design Space Exploration Problems by Composable Design Space Identification | Interactive Presentation (IP) |
1676 | Approximate Logic Synthesis of Very Large Boolean Networks | Regular Presentation |
1685 | Workload-Aware Approximate Computing Configuration | Regular Presentation |
1687 | Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design | Regular Presentation |
1696 | Leveraging Bayesian Optimization to Speed up Automatic Precision Tuning | Regular Presentation |
1700 | DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures | Regular Presentation |
1701 | Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design | Regular Presentation |
1702 | Density Enhancement of RRAMs Using a RESET Write Termination for MLC Operation | Interactive Presentation (IP) |
1720 | SPPS: Secure Policy-based Publish/Subscribe System for v2C Communication | Regular Presentation |
1725 | Sim²PIM: A Fast Method for Simulating Host Independent & PIM Agnostic Designs | Regular Presentation |
1727 | GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation | Regular Presentation |
1731 | Activation Density Based Mixed-Precision Quantization for Energy Efficient Neural Networks | Regular Presentation |
1736 | Efficient Resource Management of Clustered Multi-Processor Systems through Formal Property Exploration | Regular Presentation |
1740 | Adaptive-Learning Based Building Load Prediction for Microgrid Economic Dispatch | Interactive Presentation (IP) |
1744 | Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks | Regular Presentation |
1750 | A Fairness Conscious Cache Replacement Policy for Last Level Cache | Regular Presentation |
1751 | Operating beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management | Interactive Presentation (IP) |
1752 | Performance Analysis and Auto-tuning for SPARK In-memory Analytics | Regular Presentation |
1753 | Identification of Hardware Devices Based on Sensors and Switching Activity: A Preliminary Study | Interactive Presentation (IP) |
1756 | Real-time Private Membership Test Using Homomorphic Encryption | Regular Presentation |
1764 | A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme | Regular Presentation |
1769 | Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers | Regular Presentation |
1770 | HyGraph: Accelerating Graph Processing with Hybrid Memory-centric Computing | Regular Presentation |
1778 | Low-Latency Asynchronous Logic Design for Inference at the Edge | Interactive Presentation (IP) |
1782 | RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis | Interactive Presentation (IP) |
1784 | Paired Training Framework for Time-Constrained Learning | Regular Presentation |
1786 | TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators | Regular Presentation |
1788 | Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures | Regular Presentation |
1790 | A Differential Aging Sensor to Detect Recycled ICs Using Sub-threshold Leakage Current | Interactive Presentation (IP) |
1791 | Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality | Regular Presentation |
1792 | Printed Stochastic Computing Neural Networks | Regular Presentation |
1794 | Adaptive Generative Modeling in Resource-Constrained Environments | Regular Presentation |
1795 | AxPIKE: Instruction-level Injection and Evaluation of Approximate Computing | Interactive Presentation (IP) |
1799 | Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache | Regular Presentation |
1801 | Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs | Regular Presentation |
1807 | MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect | Regular Presentation |
1812 | Malicious Routing: Circumventing Bitstream-level Verification for FPGAs | Regular Presentation |
1815 | tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications | Regular Presentation |
1819 | FPGA Acceleration of Protein Back-Translation and Alignment | Regular Presentation |
1823 | Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line | Interactive Presentation (IP) |
1827 | Adaptive Design of Real-Time Control Systems Subject to Sporadic Overruns | Regular Presentation |
1829 | Common-Centroid Layouts for Analog Circuits: Advantages and Limitations | Regular Presentation |
1833 | Microarchitectural Timing Channels and Their Prevention on an Open-Source 64-Bit RISC-V Core | Regular Presentation |
1835 | Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification | Interactive Presentation (IP) |
1837 | Analog Layout Generation Using Optimized Primitives | Regular Presentation |
1842 | Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra | Regular Presentation |
1846 | Comparison of GPU Computing Methodologies for Safety-Critical Systems: An Avionics Case Study | Regular Presentation |
1849 | GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level | Regular Presentation |
1853 | An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes | Interactive Presentation (IP) |
1854 | A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation | Regular Presentation |
1859 | Towards Automated Detection of Higher-Order Memory Corruption Vulnerabilities in Embedded Devices | Interactive Presentation (IP) |
1861 | CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs | Regular Presentation |
1863 | NetCut: Real-Time DNN Inference Using Layer Removal | Regular Presentation |
1867 | Prediction of Thermal Hazards in a Real Datacenter Room Using Temporal Convolutional Networks | Interactive Presentation (IP) |
1869 | Duetto: Latency Guarantees at Minimal Performance Cost | Regular Presentation |
1874 | Flexible Cache Partitioning for Multi-Mode Real-Time Systems | Regular Presentation |
1876 | MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences | Regular Presentation |
1889 | FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs | Regular Presentation |
1900 | A 3-D LUT Design for Transient Error DetectionVia Inter-Tier In-Silicon Radiation Sensor | Regular Presentation |
1904 | A Deep Learning Approach of Sensor Fusion Inference at the Edge | Regular Presentation |
1906 | Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs | Interactive Presentation (IP) |
1910 | AVRNTRU: Lightweight NTRU-based Post-Quantum Cryptography for 8-Bit AVR Microcontrollers | Regular Presentation |
1913 | Resolution-Aware Deep Multi-View Camera Systems | Interactive Presentation (IP) |
1916 | QSLC: Quantization-Based, Low-Error Selective Approximation for GPUs | Regular Presentation |
1920 | PLEDGER: Embedded Whole Genome Read Mapping Using Algorithm-HW Co-design and Memory-aware Implementation | Interactive Presentation (IP) |
1926 | Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion | Regular Presentation |
1933 | System Level Verification of Phase-Locked Loop Using Metamorphic Relations | Interactive Presentation (IP) |
1935 | Automated Masking of Software Implementations on Industrial Microcontrollers | Regular Presentation |
1942 | Enhanced Detection Range for EM Side-channel Attack Probes Utilizing Co-planar Capacitive Asymmetry Sensing | Interactive Presentation (IP) |
1943 | Implementation of a MEMS Resonator-based Digital to Frequency Converter Using Artificial Neural Networks | Interactive Presentation (IP) |
1945 | OpenSerDes: An Open Source Process-Portable All-Digital Serial Link | Regular Presentation |
1953 | A 93 TOPS/Watt Near-Memory Reconfigureable SAD Accelerator for HEVC/AV1/JEM Encoding | Interactive Presentation (IP) |
1960 | GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks | Regular Presentation |
1965 | In-Memory Computing Based Accelerator for Transformer Networks for Long Sequences | Regular Presentation |
1969 | Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores | Regular Presentation |
1974 | An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory | Regular Presentation |
1978 | BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking | Interactive Presentation (IP) |
1980 | Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems | Interactive Presentation (IP) |
1981 | FeFET and NCFET for Future Neural Networks: Visions and Opportunities | Special Session Presentation |
1982 | Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta Learning Applications | Special Session Presentation |
1983 | Future Computing Platform Design: A Cross-Layer Design Approach | Special Session Presentation |
1984 | Intelligent Architectures for Intelligent Computing Systems | Special Session Presentation |
1985 | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization | Special Session Presentation |
1986 | Logic Synthesis for Generalization and Learning Addition | Special Session Presentation |
1987 | ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization | Special Session Presentation |
1988 | LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications | Special Session Presentation |
1989 | Efficiency-driven Hardware Optimization for Adversarially Robust Neural Networks | Special Session Presentation |
1990 | Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability | Special Session Presentation |
1991 | Reliable Edge Intelligence in Unreliable Environment | Special Session Presentation |
1992 | Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives | Special Session Presentation |
1993 | Mission Specification and Execution of Multidrone Systems | Special Session Presentation |
1994 | Perception Computing-Aware Controller Synthesis for Autonomous Systems | Special Session Presentation |
1995 | Closed-loop Approach to Perception in Autonomous System | Special Session Presentation |
1996 | Computing for Control and Control for Computing | Special Session Presentation |
1997 | Towards Scalable Quantum Computing | Special Session Presentation |
1998 | Quantum Computing with CMOS Technology | Special Session Presentation |
1999 | Structured Optimized Architecting of Full-Stack Quantum Systems in the NISQ Era | Special Session Presentation |
2000 | Visualizing Decision Diagrams for Quantum Computing | Special Session Presentation |
2001 | Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits | Special Session Presentation |
2002 | Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies | Special Session Presentation |
2003 | Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits | Special Session Presentation |
2004 | 3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures Using M3D Integration | Special Session Presentation |
2005 | Vertical IP Protection of the Next-Generation Devices: Quo Vadis? | Special Session Presentation |
2006 | IP Protection, Present and Future Schemes | Special Session Presentation |
2007 | Security Validation at VP-Level Using Information Flow Tracking | Special Session Presentation |
2008 | MVLOCK: A Multi-Valued Logic Locking Scheme for Future-Generation Computing Systems | Special Session Presentation |
2009 | Harnessing Security through Runtime Reconfigurable Transistors | Special Session Presentation |
2010 | From Boolean Functions to Quantum Circuits: A Scalable Quantum Compilation Flow in C++ | Special Session Presentation |
2011 | A Resource Estimation and Verification Workflow in Q# | Special Session Presentation |
2012 | HiQ-ProjectQ: Towards User-friendly and High-performance Quantum Computing on GPUs | Special Session Presentation |
2013 | Compilers for the NISQ Era | Special Session Presentation |
2014 | Remote and Stealthy Fault Attacks on Virtualized FPGAs | Special Session Presentation |
2015 | Extended Abstract: Covert Channels and Data Exfiltration from FPGAs | Special Session Presentation |
2016 | Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs | Special Session Presentation |
2017 | Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks | Special Session Presentation |
2018 | Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process | Special Session Presentation |
2019 | A Deeper Look at Energy Consumption of Lightweight Block Ciphers | Special Session Presentation |
2020 | Machine Learning Assisted Differential Distinguishers for Lightweight Ciphers | Special Session Presentation |
2021 | DNFA: Differential No-Fault Analysis of Bit Permutation Based Ciphers Assisted by Side-Channel | Special Session Presentation |
2022 | The Road towards Predictable Automotive High-Performance Platforms | Special Session Presentation |
2023 | Software Mechanisms for Controlling QoS | Special Session Presentation |
2024 | Resource Contention Avoidance Mechanisms in High-Performance Arm-based Systems | Special Session Presentation |
2025 | Admission Control for Guaranteeing E2E QoS in MPSoCs | Special Session Presentation |
2026 | Supporting System Design with Formal Performance Analysis | Special Session Presentation |
2027 | Perspectives on Emerging Computation-in-Memory Paradigms | Special Session Presentation |
2028 | Re-Engineering Computing with Memristor Devices | Special Session Presentation |
2029 | Testing of ReRAM Crossbars for In-Memory Computing | Special Session Presentation |
2030 | Design Automation for In-Memory Computing Using ReRAM Crossbar | Special Session Presentation |
2031 | Combining Memory and Logic Using Ferro-electric Transistors | Special Session Presentation |
2032 | Hardware-assisted Detection of Malware in Automotive-Based Systems | Special Session Presentation |
2033 | HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection | Special Session Presentation |
2034 | Hardware-Assisted Malware Detection Using Machine Learning | Special Session Presentation |
2035 | CASTLE: Architecting Assured System-on-Chip Firmware Integrity | Special Session Presentation |
2036 | Enabling and Supporting Car-as-a-service by Digital Twin Modeling and Deployment | Special Session Presentation |
2037 | Digital Twin Extension with Extra-Functional Properties | Special Session Presentation |
2038 | Cognitive Digital Twin for Manufacturing Systems | Special Session Presentation |
2039 | Dynamic Fault Injection into Digital Twins of Safety-critical Systems | Special Session Presentation |
2040 | Machine Learning Based Real-Time Industrial Bin-Picking: Hybrid and Deep Learning Approaches | Special Session Presentation |
2041 | Image Analytics and Machine Learning for In-situ Defects Detection in Additive Manufacturing | Special Session Presentation |
2042 | Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy | Special Session Presentation |
2043 | iCampμS: Development and Transfer Platform for Integrated Microsensor Technologies in a Connected World | Special Session Presentation |
2044 | Efficient Run-time Environments for System-level LET Programming | Special Session Presentation |
2045 | Managing Variability and Reuse of Extra-functional Control Software in CPPS | Special Session Presentation |
2046 | Strengthening Digital Twin Applications Based on Machine Learning for Complex Equipment | Special Session Presentation |
2047 | Moore’s Law and ICT Innovation in the Anthropocene | Special Session Presentation |
2048 | Few Hints towards More Sustainable Artificial Intelligence | Special Session Presentation |
2049 | Sustainable High-Performance Computing via Domain-Specific Accelerators | Special Session Presentation |
2050 | Trends in HPC Driven by the Race to Exascale | Special Session Presentation |
2051 | C-PO: A Context-Based Application-Placement Optimization for Autonomous Vehicles | Special Session Presentation |
2052 | Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive Applications | Special Session Presentation |
2053 | Anomaly Detection and Classification to Enable Self-Explainability of Autonomous Systems | Special Session Presentation |
2054 | Decentralized Autonomous Architecture for Resilient Cyber-Physical Production Systems | Interactive Presentation (IP) |
2055 | Provably Robust Monitoring of Neuron Activation Patterns | Interactive Presentation (IP) |
2056 | Automated Driving Safety - the Art of Conscious Risk Taking - Minimum Lateral Distances to Pedestrians | Special Session Presentation |
2057 | On Safety Assurance Case for Deep Learning Based Image Classification in Highly Automated Driving | Special Session Presentation |
2058 | Continuous Safety Verification of Neural Networks | Special Session Presentation |
2059 | Fünfliber-Drone: A Modular Open-Platform 18-Grams Autonomous Nano-Drone | Special Session Presentation |
2060 | Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware | Special Session Presentation |
2061 | DDI: A Novel Technology and Innovation Model for Dependable, Collaborative and Autonomous Systems | Special Session Presentation |
2062 | Systems Engineering Roadmap for Dependable Autonomous Cyber-Physical Systems | Special Session Presentation |
2063 | Timing-Predictable Vision Processingfor Autonomous Systems | Special Session Presentation |
2064 | Bounding Perception Neural Network Uncertainty for Safe Control of Autonomous Systems | Special Session Presentation |
2065 | Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems | Special Session Presentation |
2066 | Orchestration of Perception Systems for Reliable Performance in Heterogeneous Platforms | Special Session Presentation |
2067 | Quantum Supremacy Using a Programmable Superconducting Processor | Special Session Presentation |
2068 | Autonomy: One Step beyond on Commercial Aviation | Special Session Presentation |
2069 | Superconducting Quantum Materials and Systems (SQMS) – a New DOE National Quantum Information Science Research Center | Special Session Presentation |
2070 | Privacy This Unknown - the New Design Dimension of Computing Architectures | Special Session Presentation |
2071 | Programmable Photonic Circuits for Linear Processing | Special Session Presentation |
2072 | Unlocking Transformative AI with Photonic Computing | Special Session Presentation |
2073 | No Bottlenecks Allowed | Special Session Presentation |
2075 | Cyber-Physical Systems for Industry 4.0: An Industrial Perspective | Special Session Presentation |
2076 | Moore's Law Is in Trouble... More Jobs in IC Design! | Special Session Presentation |
2077 | Live Joint Q&A | Special Session Presentation |
2078 | Live Joint Q&A | Special Session Presentation |
2079 | Live Joint Q&A | Special Session Presentation |
2080 | Live Joint Q&A | Special Session Presentation |
2081 | Live Joint Q&A | Special Session Presentation |
2082 | Live Joint Q&A | Special Session Presentation |
2083 | Panel: Is EDA Ready for Cyber-Physical Systems? | Special Session Presentation |
2084 | Panel Q&A | Special Session Presentation |
2085 | Live Q&A | Special Session Presentation |
2086 | Live Q&A | Special Session Presentation |
2087 | Live Q&A | Special Session Presentation |
2088 | Silicon Photonics & Optical Computing: Chair’s Introduction | Special Session Presentation |
2089 | YPP Panel on Different Career Opportunities Having Education in Microelectronics. | Special Session Presentation |
2090 | Autonomous Systems Design: Opening Panel | Special Session Presentation |
2091 | Career Forum: Which career path to take: SWOT analysis – Room 1 | Special Session Presentation |
2092 | Career Forum: Which career path to take: SWOT analysis – Room 2. | Special Session Presentation |
2093 | Career Forum: Which career path to take: SWOT analysis – Room 3 | Special Session Presentation |
2094 | Career Forum: Which career path to take: SWOT analysis – Room 4 | Special Session Presentation |
2095 | Career Forum: Which career path to take: SWOT analysis – Room 5 | Special Session Presentation |
3060 | Welcome Addresses | Regular Presentation |
3061 | Presentation of Awards | Regular Presentation |
3062 | Plenary Keynote 1: TBD | Regular Presentation |
3063 | Plenary Keynote 2: TBD | Regular Presentation |
5020 | Opening of the PhD Forum | Regular Presentation |
5030 | Exploiting Error Resilience of Iterative and Accumulation based Algorithms for Hardware Efficiency | Regular Presentation |
5031 | Improving Energy Efficiency of Neural Networks | Regular Presentation |
5032 | Design, Implementation and Analysis of Efficient Hardware-based Security Primitives | Regular Presentation |
5036 | Formal Abstraction and Verification of Analog Circuits | Regular Presentation |
5039 | Optimization Tools for ConvNets on the Edge | Regular Presentation |
5040 | Design Space Exploration in High Level Synthesis | Regular Presentation |
5041 | Reliability Improvement of STT-MRAM Cache Memories in Data Storage Systems | Regular Presentation |
5043 | Enabling Logic-Memory Synergy using Integrated Non-Volatile Transistor Technologies for Energy-Efficient Computing | Regular Presentation |
5044 | Hardware Security in DRAMs and Processor Caches | Regular Presentation |
5050 | Real-Time High-Performance Computing for Embedded Control Systems | Regular Presentation |
5051 | Less is more: efficient hardware design through Approximate Logic Synthesis | Regular Presentation |
5052 | LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects | Regular Presentation |
5053 | Energy Efficient and Runtime based Approximate Computing Techniques for Image Compression Application: An Integrated Approach Covering Circuit to Algorithmic Level | Regular Presentation |
5055 | Thesis: Performance and Physical Attack Security of Lattice-Based Cryptography | Regular Presentation |
5056 | Amoeba-inspired System Controller on IoT Edge | Regular Presentation |
5057 | Monitoring and Controlling Interconnect Contention in Critical Real-Time Systems | Regular Presentation |
5059 | Reliability considerations in the use of high-performance processors in safety-critical systems | Regular Presentation |
5060 | Hardware Security Evaluation of IoT Embedded Applications | Regular Presentation |
5061 | A Computer-aided Design Space Exploration for Dependable Circuits | Regular Presentation |
5063 | Robust and Energy-Efficient Deep Learning Systems | Regular Presentation |
5064 | Automated Design of Approximate Accelerators | Regular Presentation |
5065 | Next Generation Design For Testability, Debug and Reliability Using Formal Techniques | Regular Presentation |
5067 | Design Automation for Field-coupled Nanotechnologies | Regular Presentation |
5068 | Hardware and Software Techniques for Securing Intelligent Cyber-Physical Systems | Regular Presentation |
8003 | Nano Security: From Nano-Electronics to Secure Systems | Regular Presentation |
8004 | Project Overview for Step-UP!CPS – Process, Methods and Technologies for Updating Safety-critical Cyber-physical Systems | Interactive Presentation (IP) |
8006 | VeriDevOps: Automated Protection and Prevention to Meet Security Requirements in DevOps | Interactive Presentation (IP) |
8007 | EVEREST: A Design Environment for Extreme-scale Big Data Analytics on Heterogeneous Platforms | Regular Presentation |
8008 | The up2DATE Baseline Research Platforms | Interactive Presentation (IP) |
8009 | GPU4S: Major Project Outcomes, Lessons Learnt and Way Forward | Regular Presentation |
10330 | MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs | Regular Presentation |
10331 | MELODI: A Mass e-Learning System for Design, Test, and Prototyping of Digital Hardware | Regular Presentation |
10336 | DeFacto: Design Automation for Smart Factories | Regular Presentation |
10339 | Nyuzi: An Open Source GPGPU for Graphics, Enhanced with OpenCL Compiler for Calculations | Regular Presentation |
10344 | CATANIS: CAD Tool for Automatic Network Synthesis | Regular Presentation |
10345 | FPGA Acceleration of Apache Spark SQL Using Apache Arrow and Fletcher | Regular Presentation |
10346 | ELSA: Formal Abstraction and Verification of Analog Circuits | Regular Presentation |
10347 | Brook SC: High-level Certification-friendly Programming for GPU-powered Safety Critical Systems | Regular Presentation |
10348 | Euclid-NIR GPU: An On-board Processing GPU-accelerated Space Case Study Demonstrator | Regular Presentation |
10349 | Skeletor: An Open Source EDA Tool Flow from Hierarchy Specification to HDL Development | Regular Presentation |
10350 | MAEVE: 3D Human Motion Analysis Evaluation from Video at the Edge | Regular Presentation |
10351 | Greyhound: Deep Fuzzing IoT Wireless Protocols | Regular Presentation |
10352 | Modular hardware and software platform for the rapid implementation of ASIC-based bioanalytical test systems | Regular Presentation |
10353 | SRAM-PUF: Platform for Acquisition of SRAM-based PUFs from Micro-Controllers | Regular Presentation |
10355 | Design Automation for Extended Burst-Mode Automata in Workcraft | Regular Presentation |
10357 | HardBlock: Demonstrator of physically binding an IoT device to a non-fungible token in Ethereum blockchain | Regular Presentation |
10359 | LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development | Regular Presentation |
10360 | TaPaSCo: The Open-Source Task-Parallel System Composer Framework | Regular Presentation |
10361 | JOINTER: JOining flexIble moNitors wiTh hEterogeneous architectuRes | Regular Presentation |
10362 | SHM-LSNN: Demonstration of a brain-inspired structural health monitoring system | Regular Presentation |
10363 | MDD2FPGA: ROS-based Experimental Environment towards Model-Driven-Development with FPGA | Regular Presentation |
10364 | 3D-Mem-Therm: A fast, accurate 3D Memory thermal simulator | Regular Presentation |
10367 | Neuromuscular Synergies based Cyber-Physical Platform for the Fast Lack of Balance Recognition | Regular Presentation |
18000 | Future of HPC: Diversifying Heterogeneity | Special Session Presentation |
18001 | Distributed Grid Computing Manager Covering Waste Heat Reuse Constraints | Special Session Presentation |
18002 | Coyote: An Open Source Simulation Tool to Enable RISC-V in HPC | Special Session Presentation |
18003 | From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience | Special Session Presentation |
18004 | A Data Center Demand Response Policy for Real-World Workload Scenarios in HPC | Special Session Presentation |
18005 | Storage Class Memory with Computing Row Buffer: A Design Space Exploration | Special Session Presentation |
18006 | Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors | Special Session Presentation |
18007 | Accelerating Data Center Decarbonization and Maximizing Renewable Usage with Grid Edge Solutions | Special Session Presentation |
18008 | Heterogeneous Computing Systems for Complex Scientific Discovery Workflows | Special Session Presentation |
18072 | Enabling Early and Fast Thermal Simulation for 3D Multi-Die System Designs | Not decided yet |
18073 | Future Vision of Altair for EDA Applications | Not decided yet |
18074 | Exhibition Keynote - Digital Twin: the Future Is Now | Not decided yet |
18075 | Book Publishing 101: The Why, How and What | Not decided yet |
18076 | Andes RISC-V Processor IP Solutions | Not decided yet |
18077 | Automating Tiny Neural Network Design with MCU Deploy-ability in the Loop | Not decided yet |
18078 | Earlier SoC Integration with a Multidimensional Design Reuse | Not decided yet |
18079 | Extending the Role of Test to meet Automotive Safety and Security Requirements | Not decided yet |