Topic: T3 Design-for-Test, Test Infrastructures, Test Standards

Architectures and solutions for design for test, diagnosis, debug, post silicon validation; BIST and embedded test; Power-On Self-Test; Test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, NoC, Microprocessors; Test Infrastructures for Secure Devices; Test principles and methods for design-for-trust; ATE architectures; Test Standards (JTAG, IJTAG, 1500, P1838)

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Ozgur Sinanoglu, New York University - Abu Dhabi, AE, Contact

Members:

• Alberto Bosio, LIRMM - University of Montpellier 2, FR, Contact
• Krishnendu Chakrabarty, Duke University, US, Contact
• Rohit Kapur, Synopsys, US, Contact
• Erik Larsson, Lund University, SE, Contact
• Jerzy Tyszer, Poznan University of Technology, PL, Contact