Technical Programme Committee 2017

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Track D: Design Methods and Tools (click to open)

This track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Ayse Kivilcim Coskun, Boston University, US, Contact

Topics

D1 System Specification and Modelling (click to open)

Chair: Ingo Sander, Royal Institute of Technology, SE, Contact

Co-Chair: Andreas Gerstlauer, University of Texas at Austin, US, Contact

Topic Members (click to open)

  • Timo Hämäläinen, Tampere University of Technology, FI, Contact
  • Michael Hübner, Ruhr-Universität Bochum, DE, Contact
  • Jorn W. Janneck, Lund University, SE, Contact
  • Frédéric Mallet, Université Nice Sophia Antipolis, FR, Contact
  • Gianluca Palermo, Politecnico di Milano, IT, Contact
  • Laurence Pierre, TIMA, FR, Contact
  • Martin Radetzki, Institut für Technische Informatik, DE, Contact
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact

Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, High-Level Synthesis and Optimization (click to open)

Chair: Andreas Herkersdorf, Technische Universität München, DE, Contact

Co-Chair: Nikil Dutt, University of California, Irvine, US, Contact

Topic Members (click to open)

  • Alberto A. Barrio del, Universidad Complutense de Madrid: UCM, ES, Contact
  • Lars Bauer, KIT, DE, Contact
  • Kiyoung Choi, Seoul National Univ., KR, Contact
  • Suhaib A. Fahmy, University of Warwick, GB, Contact
  • Michael Glass, Universität Ulm, DE, Contact
  • Kim Grüttner, OFFIS - Institut für Informatik, DE, Contact
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Fadi Kurdahi, University of California at Irvine, US, Contact
  • Roman Lysecky, University of Arizona, US, Contact
  • Christian Plessl, University of Paderborn, DE, Contact
  • Thomas Preußer, Technische Universität Dresden, DE, Contact
  • David Thomas, Imperial College London, GB, Contact
  • Daniel Ziener, Hamburg University of Technology, DE, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; hw/sw design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Elena Ioana Vatajelu, TIMA Laboratory, FR, Contact

Co-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Flavio M. de Paula, IBM Corporation, US, Contact
  • Adrian Evans, iRoC Technologies, FR, Contact
  • Daniel Grosse, University of Bremen, DE, Contact
  • Graziano Pravadelli, EDALab, IT, Contact
  • Alper Sen, Bogazici University, TR, Contact
  • Shobha Vasudevan, University of Illinois at Urbana-Champaign, US, Contact
  • Sara Vinco, Politecnico di Torino, IT, Contact
  • Li Wang, UC Santa Barbara, US, Contact

Simulation-based validation and verification; acceleration-driven and emulation-based validation; post-silicon verification; online checkers and runtime verification targeting new and traditional architectures and addressing the verification challenge at any level, from system to circuit level; diagnosing and debugging solutions for any of the verification platforms above; testbenches, checkers, assertions and monitor generation for verification; multi-domain simulation techniques; validation of cyber-physical systems, SoCs and emerging architectures.

D4 Formal Methods and Verification (click to open)

Chair: Christoph Scholl, University Freiburg, DE, Contact

Co-Chair: Armin Biere, Universitaet Linz, AT, Contact

Topic Members (click to open)

  • Alberto Griggio, Fondazione Bruno Kessler, IT, Contact
  • Marijn Heule, The University of Texas at Austin, US, Contact
  • Barbara Jobstmann, VERIMAG, FR, Contact
  • Wenchao Li, Boston University, US, Contact
  • Julien Schmaltz, Eindhoven University of Technology, NL, Contact
  • Daryl Stewart, ARM, GB, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, SoCs, and cores; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: André Ivanov, , CA, Contact

Co-Chair: Georges Gielen, Katholieke Universiteit Leuven, BE, Contact

Topic Members (click to open)

  • Josep Altet, Universitat Politècnica de Catalunya, ES, Contact
  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Christoph Grimm, TU Vienna, AT, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
  • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
  • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
  • marie-Minerve Louerat, UNiversity Pierre & Marie Curie, LIP6, FR, Contact
  • Shahriar Mirabbasi, UBC, CA, Contact
  • Jaijeet Roychowdhury, University of California at Berkeley, US, Contact
  • Manoj Sachdev, University of Waterloo, CA, Contact
  • Shreyas Sen, Purdue University, US, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel, BE, Contact

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

D6 Power Modeling, Optimization and Low-Power Design (click to open)

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR, Contact

Topic Members (click to open)

  • Andrea Bartolini, University of Bologna, IT, Contact
  • Andrea Calimera, Politecnico di Torino, IT, Contact
  • William Fornaciari, Politecnico di Milano, IT, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Jae-Joon Kim, POSTECH, KR, Contact
  • Hiroshi Nakamura, University of Tokyo, JP, Contact
  • Alberto Nannarelli, DTU, DK, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • Salvatore Rinaudo, STMicroelectronics, IT, Contact
  • Martha Johanna Sepulveda Florez, Technical University of Munich, DE, Contact
  • Donghwa Shin, Department of Computer Engineering, Yeungnam University, KR, Contact
  • Sheldon Tan, UC Riverside, US, Contact
  • Pascal Vivet, CEA-Leti, FR, Contact
  • Yanzhi Wang, Syracuse University, US, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact
  • Shusuke Yoshimoto, Osaka University, JP, Contact

Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

D7 Network on Chip (click to open)

Chair: Luca Carloni, Columbia University, US, Contact

Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Fabien Clermidy, COMMISSARIAT A L' ENERGIE ATOMIQUE, FR, Contact
  • Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact
  • Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
  • Natalie Enright Jerger, University of Toronto, CA, Contact
  • Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
  • Paul Gratz, Texas A&M University, US, Contact
  • Andreas Hansson, ARM Ltd, GB, Contact
  • Ravi Iyer, Intel, US, Contact
  • Axel Jantsch, Technische Universität Wien, AT, Contact
  • Ajay Joshi, Boston University, US, Contact
  • John Kim, KAIST, KR, Contact
  • Tushar Krishna, GeorgiaTech, US, Contact
  • Riccardo Locatelli, STMicroelectronics, FR, Contact
  • Fernando Moraes, PUC-RS, BR, Contact
  • Umit Ogras, Arizona State University, US, Contact
  • Jiang Xu, Hong Kong University of Science and Technology, CN, Contact

Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security and power management; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

D8 Architectural and Microarchitectural Design (click to open)

Chair: Cristina Silvano, Politecnico di Milano, IT, Contact

Co-Chair: Elaheh Bozorgzadeh, University of California, Irvine, US, Contact

Topic Members (click to open)

  • Mladen Berekovic, Technische Universität Braunschweig, DE, Contact
  • Christos Bouganis, Imperial College, GB, Contact
  • Ramon Canal, Universitat Politècnica de Catalunya (UPC), ES, Contact
  • Jeronimo Castrillon, TU Dresden, Germany, DE, Contact
  • Francisco Cazorla, BSC, ES, Contact
  • Giuseppe Desoli, STMicroelctronics, IT, Contact
  • Pedro C. Diniz, USC Information Sciences Institute, US, Contact
  • Leandro Fiorin, IBM Research, NL, Contact
  • Houman Homayoun, George Mason University, US, Contact
  • Georgios Keramidas, Think Silicon S.A./Technological Educational Institute of Western Greece, GR, Contact
  • Yun (eric) Liang, Peking University, CN, Contact
  • Andrea Marongiu, ETH Zurich, CH, Contact
  • Gokhan Memik, Northwestern University, US, Contact
  • Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact
  • Laura Pozzi, USI Lugano, CH, Contact
  • Toshinori Sato, Fukuoka University, JP, Contact
  • Olivier Sentieys, CAIRN,IRISA, FR, Contact
  • Zili Shao, Hong Kong Polytechnic University, HK, Contact
  • Antonino Tumeo, Pacific Northwest National Laboratory, US, Contact
  • Cong Xu, HP Lab, US, Contact
  • Sotirios Xydis, National Technical University of Athens, GR, Contact

Architectural and micro-architectural design techniques; memory systems; power and energy efficient architectures; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, security, timing predictability.

D9 Temperature and Variability Aware System Design and Optimization (click to open)

Chair: Giovanni Ansaloni, University of Lugano, CH, Contact

Co-Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

Topic Members (click to open)

  • Giovanni Beltrame, École Polytehcnique de Montréal, CA, Contact
  • Siddharth Garg, New York University, US, Contact
  • Timothy Jones, University of Cambridge, GB, Contact
  • Georgios Karakonstantis, Queen's University Belfast, GB, Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • Seda Memik, Northwestern University, US, Contact
  • Mohamed Sabry, Stanford, US, Contact
  • Rene van Leuken, TU Delft, NL, Contact
  • Pieter Weckx, IMEC vzw, BE, Contact
  • Kai-Chiang Wu, National Chiao Tung University, ES, Contact

Methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects; design and run-time thermal, variability and reliability management of SoCs and multi-core platforms (both at hardware and software level); modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.

D10 Reconfigurable Computing (click to open)

Topic Members (click to open)

    Reconfigurable computing platforms and architectures; heterogeneous platforms (FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high performance and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.

    D11 Logical and Physical Analysis and Design (click to open)

    Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact

    Co-Chair: Tiziano Villa, University of Verona, IT, Contact

    Topic Members (click to open)

    • Anna Bernasconi, Universita' di Pisa, IT, Contact
    • Luca Daniel, Massachusetts Institute of Technology, US, Contact
    • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
    • Patrick Groeneveld, Synopsys, US, Contact
    • Jose Monteiro, , PT, Contact
    • Rajeev Murgai, Synopsys, IN, Contact
    • Alessandra Nardi, Cadence Design Systems, US, Contact
    • Cliff Sze, IBM Austin Research Laboratory, US, Contact
    • Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact

    Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments. Parasitic and variation-aware extraction for on-chip interconnect and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.

    D12 Emerging Technologies for Future Computing (click to open)

    Chair: Aida Todri, CNRS, Fr, Contact

    Co-Chair: Subhasish Mitra, Stanford University, US, Contact

    Topic Members (click to open)

    • Deji Akinwande, University of Texas, US, Contact
    • Elena Gnani, University Bologna, IT, Contact
    • Marc Heyns, IMEC, BE, Contact
    • Guilhem Larrieu, CNRS-LAAS, FR, Contact
    • Cristell Maneux, University of Bordeaux, FR, Contact
    • Dmitri Maslov, National Science Foundation, US, Contact
    • Arijit Raychowdhury, Georgia Institute of Technology, US, Contact
    • Heike Riel, IBM Research - Zurich, CH, Contact
    • Max Shulaker, Stanford U, US, Contact
    • Walter Weber, Namlab gGmbH, DE, Contact

    Modeling, circuit design and design automation flows for future computing including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (TSV modeling and design space exploration).

    D13 Emerging Technologies for Future Memories (click to open)

    Chair: Jean-Michel Portal, IM2NP, FR, Contact

    Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact

    Topic Members (click to open)

    • Luca Amaru, Synopsys, US, Contact
    • Costin Anghel, Institut supérieur d'électronique de Paris, FR, Contact
    • Bastien Giraud, CEA-Leti, Minatec, FR, Contact
    • Arne Heittmann, RWTH Aachen University, DE, Contact
    • Daniele Ielmini, Politecnico di Milano, IT, Contact
    • Kyungsu Kang, EPFL, CH, Contact
    • Luca Larcher, Università di Modena e Reggio Emilia, IT, Contact
    • Hai Li, Dept. of Electrical and Computer Engineering University of Pittsburgh, US, Contact
    • Pascal Meinerzhagen, Intel Labs, US, Contact
    • Tajana Simunic Rosing, UCSD, US, Contact
    • Stefan Slesazeck, NaMLab gGmbH, DE, Contact
    • Naveen Verma, Princeton, US, Contact
    • Hao Yu, Nanyang Technical University, SG, Contact
    • Weisheng Zhao, Beihang Univ., CN, Contact

    Modeling, circuit design and design automation flows for future data storage including: non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots etc.); advances in flash memory technology; memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile cache etc.); memory management techniques for emerging memories.


    Track A: Application Design (click to open)

    This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as applications of specific design and test methodologies. Contributions should illustrate state-of-the-art or record-breaking designs, which will provide viable solutions in tomorrow's silicon and embedded systems. In topic A8, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.

    Track Chair: Ian O'Connor, Ecole Centrale de Lyon, FR, Contact

    Topics

    A1 Green Computing Systems (click to open)

    Chair: Andreas Burg, EPFL, CH, Contact

    Co-Chair: Muhammad Shafique, Technische Universität Wien, AT, Contact

    Topic Members (click to open)

    • Baris Aksanli, San Diego State University, US, Contact
    • Luca Benini, ETHZ, CH, Contact
    • Vivek De, Intel, US, Contact

    Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for energy-efficient computing, virtualization, energy-efficient memory, processor, or communication architectures including non-volatile memory architectures and their use as storage components in datacenters, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in smart-grids.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Steffen Paul, Universität Bremen, DE, Contact

    Co-Chair: Theo Theocharides, University of Cyprus, CY, Contact

    Topic Members (click to open)

    • Marcello Coppola, STMicroelectronics, FR, Contact
    • Christian Drewes, Intel Mobile Communications GmbH, DE, Contact
    • Ioannis Papaefstathiou, Technical University of Crete, GR, Contact

    Application design experiences for communication, multimedia and consumer systems such as smartphones, smart-books/tablets including digital integrated circuit design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor Systems on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

    A3 Automotive Systems and Smart Energy Systems (click to open)

    Chair: David Boyle, Imperial College London, GB, Contact

    Co-Chair: Davide Brunelli, DISI - University of Trento, IT, Contact

    Topic Members (click to open)

    • Michele Magno, ETHZ Zurich, CH, Contact
    • Geoff Merrett, University of Southampton, GB, Contact
    • Massimo Poncino, Politecnico di Torino, IT, Contact
    • Sebastian Steinhorst, Technical University of Munich, DE, Contact
    • Bart Vermeulen, NXP Semiconductors, NL, Contact

    Design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Finally, topics of interest are also hardware solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

    A4 Healthcare, Wellness and Assistive Technology (click to open)

    Chair: Francisco Rincon, EPFL, CH, Contact

    Co-Chair: Olivier Romain, ENSEA, FR, Contact

    Topic Members (click to open)

    • Luca Fanucci, University of Pisa, IT, Contact
    • Elisabetta Farella, Fondazione Bruno Kessler, IT, Contact
    • Joaquín Recas, Computense University of Madrid, ES, Contact
    • Sylvie Renaud, IMS Bordeaux, FR, Contact

    Design experiences covering the use of IoT, wireless body sensor networks, assistive and wearable technologies for healthcare, rehabilitation and wellness. This includes but is not limited to: technologies for ultra-low/zero power systems for personal vital sign monitoring (such as heart rate, fitness devices); body area networks; mobile systems for motor disorder assessment and rehabilitation; wearable computing technologies, devices and systems for personal health and personalized medicine; ambient assisted living technologies; innovative implantable miniaturized sensors and actuators; smart spaces for elderly and impaired users;

    A5 Secure Systems (click to open)

    Chair: Tim Güneysu, University of Bremen, DE, Contact

    Co-Chair: Wieland Fischer, Infineon, DE, Contact

    Topic Members (click to open)

    • Lejla Batina, Radboud University Nijmegen, NL, Contact
    • Cheng Cheng-Mou (Doug), National Taiwan University, TW, Contact
    • Jean-Luc Danger, Telecom ParisTech, FR, Contact
    • Elke De Mulder, Cryptography Research, US, Contact
    • Viktor Fischer, Laboratoire Hubert Curien, FR, Contact
    • Aurélien Francillon, EURECOM, FR, Contact
    • Kris Gaj, George Mason University, US, Contact
    • Frank K. Gürkaynak, ETH Zürich, CH, Contact
    • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
    • Mehran Mozaffari Kermani, RIT, US, Contact
    • Sandip Kundu, University of Massachusetts, US, Contact
    • Roel Maes, Intrinsic-ID, NL, Contact
    • Stefan Mangard, TU Graz, AT, Contact
    • Marcel Medwed, NXP Semiconductors, AT, Contact
    • Filippo Melzani, STMicroelectronics, IT, Contact
    • Nele Mentens, ESAT/COSIC and iMinds, KU Leuven, BE, Contact
    • Amir Moradi, Ruhr University Bochum, DE, Contact
    • David Naccache, ENS, FR, Contact
    • David Oswald, University of Birmingham, GB, Contact
    • Ilia Polian, Universität Passau, DE, Contact
    • Jean-Pierre Seifert, Technische Universität Berlin, DE, Contact
    • Sergei Skorobogatov, University of Cambridge, GB, Contact
    • Marc Stöttinger, Continental, DE, Contact
    • Mostafa Taha, Western University, CA, Contact
    • Mark M. Tehranipoor, University of Florida, US, Contact

    Design experiences on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random number generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including Physically Unclonable Functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: Praveen Raghavan, IMEC, BE, Contact

    Co-Chair: Christian Weis, University of Kaiserslautern, DE, Contact

    Topic Members (click to open)

    • Veit Kleeberger, Infineon Technologies AG, DE, Contact
    • Antonio Miele, Politecnico di Milano, IT, Contact
    • Wenjing Rao, University of Illinois at Chicago, US, Contact
    • Sanghamitra Roy, Utah State University, US, Contact
    • Chiara Sandionigi, CEA, FR, Contact

    Design experiences in the area of reliable and variability-aware adaptive systems for practical and industrial applications. The scope of this topic includes, but is not limited to, reliable and reconfigurable system development and optimization, practical application mechanisms and use cases that compensate reliability issues, such as aging, variability and temperature, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Applications of Emerging Technologies (click to open)

    Chair: Andy M. Tyrrell, University of York, GB, Contact

    Co-Chair: Yu Wang, Tsinghua University, CN, Contact

    Topic Members (click to open)

    • Armin Alaghi, University of Washington, US, Contact
    • Michal Bidlo, Brno University of Technology, CZ, Contact
    • Pantelis Georgious, Imperial College London, GB, Contact
    • Jim Harkin, University of Ulster, GB, Contact
    • Tsung-Yi Ho, National Tsing Hua University, TW, Contact
    • Li Jiang, Shanghai JiaoTong University, CN, Contact
    • Paul Kaufmann, Paderborn University, DE, Contact
    • Bing Li, Technische Universität München, DE, Contact
    • Yongpan Liu, Tsinghua University, CN, Contact
    • Lukas Sekanina, Brno University of Technology, CZ, Contact
    • Martin A. Trefzer, University of York, GB, Contact
    • Hailong Yao, Tsinghua University, CN, Contact

    Applications of and design methods for systems based on future and emerging technologies including: biologically-based or biologically-inspired computing systems; Bio-MEMS, lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical etc.)

    A8 Industrial Experiences Brief Papers (click to open)

    Chair: Raphaël David, CEA LIST, FR, Contact

    Co-Chair: Eugenio Villar, University of Cantabria, ES, Contact

    Topic Members (click to open)

    • Mario Diaz-Nava, STMicroelectronics, FR, Contact
    • Ahmed Jerraya, CEA Leti, FR, Contact
    • Norbert Wehn, TU Kaiserslautern, DE, Contact
    • Huafeng Yu, Boeing, US, Contact

    Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


    Track T: Test and Robustness (click to open)

    Covering all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.

    Track Chair: Giorgio Di Natale, LIRMM, FR, Contact

    Topics

    T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability (click to open)

    Chair: Mehdi Tahoori, Karlsruhe Institute of Technology, DE, Contact

    Co-Chair: Said Hamdioui, Delft University of Technology, NL, Contact

    Topic Members (click to open)

    • Vikas Chandra, ARM, US, Contact
    • Seiji Kajihara, Kyushu Institute of Technology, JP, Contact
    • Bram Kruseman, NXP Semiconductors Netherlands BV, NL, Contact
    • Hans Manhaeve, Ridgetop Europe, BE, Contact
    • Jose Pineda de Gyvez, NXP Semiconductors, NL, Contact
    • Rosa Rodriguez, UPC, ES, Contact
    • Antonio Rubio, Universitat Politècnica de Catalunya (UPC), ES, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms in conventional, advanced and emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT…); defect-based fault analysis; reliability analysis and modeling at device, circuit and component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit and component level;

    T2 Test Generation, Simulation and Diagnosis (click to open)

    Chair: Wu-Tung Cheng, Mentor Graphics, US, Contact

    Co-Chair: M. Sonza Reorda, Politecnico di Torino, IT, Contact

    Topic Members (click to open)

    • Jacob A. Abraham, The University of Texas at Austin, US, Contact
    • Davide Appello, ST Microelectronics, IT, Contact
    • Stephan Eggersglüß, University of Bremen, DE, Contact
    • Martin Keim, Mentor Graphics, US, Contact
    • Huawei Li, Institute of Computing Technology, CAS, CN, Contact
    • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

    Algorithms for test pattern generation (TPG); TPG for delay and small-delay faults; TPG for low power; Algorithms for test compression and compaction; ATPGs; Fault simulation; Diagnosis; Power Issues in Testing; Test generation for: Microprocessors, Memories, FPGAs and regular structures; Algorithms for board and system test; Volume diagnosis and yield analysis

    T3 Design-for-Test, Test Infrastructures, Test Standards (click to open)

    Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

    Co-Chair: Ozgur Sinanoglu, New York University - Abu Dhabi, AE, Contact

    Topic Members (click to open)

    • Alberto Bosio, LIRMM - University of Montpellier 2, FR, Contact
    • Krishnendu Chakrabarty, Duke University, US, Contact
    • Rohit Kapur, Synopsys, US, Contact
    • Erik Larsson, Lund University, SE, Contact
    • Jerzy Tyszer, Poznan University of Technology, PL, Contact

    Architectures and solutions for design for test, diagnosis, debug, post silicon validation; BIST and embedded test; Power-On Self-Test; Test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, NoC, Microprocessors; Test Infrastructures for Secure Devices; Test principles and methods for design-for-trust; ATE architectures; Test Standards (JTAG, IJTAG, 1500, P1838)

    T4 System-Level Reliability Design, Analysis and On-line Test (click to open)

    Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

    Co-Chair: Jaume Abella, Barcelona Supercomputing Center, ES, Contact

    Topic Members (click to open)

    • Lorena Anghel, TIMA Laboratory, FR, Contact
    • Jie Han, University of Alberta, CA, Contact
    • Viacheslav Izosimov, The Royal Institute of Technology (KTH), SE, Contact
    • Maksim Jenihhin, Tallinn University of Technology, EE, Contact
    • Cecilia Metra, University of Bologna, IT, Contact
    • Brett Meyer, McGill University, CA, Contact
    • Maria Michael, University of Cyprus, CY, Contact
    • Kazutero Namba, Chiba University, JP, Contact
    • Mihalis Psarakis, , GR, Contact
    • Pedro Reviriego, Universidad Antonio de Nebrija, ES, Contact
    • Ioannis Sourdis, Chalmers Univeristy of Technology, SE, Contact
    • Andreas Steininger, Vienna University of Technology, AT, Contact

    Fault models: Permanent, Transient and Soft Errors; Dependability Evaluation; Space-, Time- and Information-redundancy based dependability solutions; Highly-Available Systems; Reliable, Secure and Fail-Safe System Design; HW/SW solutions for on-line fault detection, tolerance, recovery and aging mitigation; Countermeasures Against Fault Attacks.

    DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

    Chair: André Ivanov, , CA, Contact

    Co-Chair: Georges Gielen, Katholieke Universiteit Leuven, BE, Contact

    Topic Members (click to open)

    • Josep Altet, Universitat Politècnica de Catalunya, ES, Contact
    • Manuel Barragan, TIMA Laboratory, FR, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Deukhyoun Heo, Washington State University, US, Contact
    • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
    • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
    • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
    • marie-Minerve Louerat, UNiversity Pierre & Marie Curie, LIP6, FR, Contact
    • Shahriar Mirabbasi, UBC, CA, Contact
    • Jaijeet Roychowdhury, University of California at Berkeley, US, Contact
    • Manoj Sachdev, University of Waterloo, CA, Contact
    • Shreyas Sen, Purdue University, US, Contact
    • Gerd Vandersteen, Vrije Universiteit Brussel, BE, Contact

    Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.


    Track E: Embedded Systems Software (click to open)

    It is devoted to modeling, analysis, design and deployment of embedded software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked and dependable systems.

    Track Chair: Franco Fummi, Universität Verona, IT, Contact

    Topics

    E1 Real-time, Networked, and Dependable Systems (click to open)

    Chair: Rodolfo Pellizzoni, University of Waterloo, CA, Contact

    Co-Chair: Kai Lampka, Elektrobit Automotive GmbH, DE, Contact

    Topic Members (click to open)

    • Sebastian Altmeyer, University of Amsterdam, NL, Contact
    • Iain Bate, University of York, GB, Contact
    • Marko Bertogna, University of Modena, IT, Contact
    • Dionisio de Niz, Carnegie Mellon University, US, Contact
    • Rolf Ernst, Technische Universität Braunschweig, DE, Contact
    • Gerhard Fohler, TU Kaiserslautern, DE, Contact
    • Nan Guan, Hong Kong Polytechnic University, HK, Contact
    • Dorin Maxim, ISEP, PT, Contact
    • Florian Pölzlbauer, Virtual Vehicle, AT, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; software for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications.

    E2 Compilers and Software Synthesis for Embedded Systems (click to open)

    Chair: Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact

    Co-Chair: Aviral Shrivastava, Arizona State University, US, Contact

    Topic Members (click to open)

    • Florian Brandner, Télécom ParisTech, FR, Contact
    • Oliver Bringmann, Universität Tübingen, DE, Contact
    • Bjorn De Sutter, Ghent University, BE, Contact
    • Tony Givargis, University of California, Irvine, US, Contact
    • Reiley Jeyapaul, ARM, US, Contact
    • Jingling Xue, University of New South Wales, AU, Contact

    Compiler support for multi-core/many-core architectures, GPUs, CGRAs, FPGAs, accelerators in heterogeneous computing platforms, memory hierarchy including caches, scratchpad, and non-volatile memories; Code analysis, optimization, and generation for different metrics (e.g., performance, power/energy, code/data size, reliability, security, WCET, etc.); Just-in-time compilation, interpreters, binary translation; Compiler support for enhanced debugging, profiling, and traceability; Software tools and techniques for design space exploration (compilers, simulators, synthesis tools); Compilation infrastructures for high-level synthesis and domain-specific or streaming languages for embedded systems; Software synthesis for IoT, wearables, cyber-physical systems, programmable microfluidics.

    E3 Model-based Design and Verification for Embedded Systems (click to open)

    Chair: Petru Eles, Linköping University, SE, Contact

    Co-Chair: Alain Girault, INRIA, FR, Contact

    Topic Members (click to open)

    • Borzoo Bonakdarpour, McMaster University, CA, Contact
    • Ylies Falcone, University Grenoble Alpes, FR, Contact
    • Sebastian Fischmeister, University of Waterloo, CA, Contact
    • Frank Slomka, Ulm University, DE, Contact
    • Oleg Sokolsky, University of Pennsylvania, US, Contact
    • Lothar Thiele, ETH Zurich, CH, Contact

    Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.

    E4 Embedded Software Architectures (click to open)

    Chair: Hiroyuki Tomiyama, Ritsumeikan University, JP, Contact

    Co-Chair: Akash Kumar, Technische Universitaet Dresden, DE, Contact

    Topic Members (click to open)

    • Mohammad Abdullah Al Faruque, University of California Irvine, US, Contact
    • Jian-Jia Chen, TU Dortmund, DE, Contact
    • Orlando Moreira, Ericsson, NL, Contact
    • Frédéric Pétrot, TIMA Laboratory, Grenoble Institute of Technology, FR, Contact
    • Tanguy Risset, Insa-Lyon, FR, Contact
    • Gunar Schirner, Norhteastern University, US, Contact
    • Sungjoo Yoo, Seoul National University, KR, Contact

    Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for approximate computation and accelerators; Software architectures for low power and temperature awareness.

    E5 Software architectures for Cyber-Physical Systems (click to open)

    Chair: Paul Pop, Technical University of Denmark, DK, Contact

    Co-Chair: Karl-Erik Arzen, Lund University, SE, Contact

    Topic Members (click to open)

    • Radu Grosu, Vienna University of Technology, AT, Contact
    • Shiyan Hu, Michigan Technological University, US, Contact
    • Thomas Nolte, MRTC/Malardalen University, SE, Contact
    • Qi Zhu, UCR, US, Contact

    Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis