Date: Thursday 30 March 2017
Time: 11:00 - 12:30
Location / Room: 4BC

Organisers:
Pierre-Emmanuel Gaillardon,, The University of Utah at Salt Lake City, US
Mathias Soeken, EPFL, CH

Chair:
Mathias Soeken, EPFL, CH

Co-Chair:
Ian O’Connor, Ecole Centrale de Lyon, FR

In this hot topic session, we demonstrate how design automation enables emerging technologies. Four talks will be provided. The first talk will review how logic synthesis has and is still enabling today's technologies and will also outline the requirements of design automation for the technologies of tomorrow. The other three talks present several emerging technologies, such as carbon nanotubes, spin wave devices, quantum-dot cellular automata, nanomagnetic logic and quantum computing, and illustrate how design automation plays a central role in their development.

Time	Label	Presentation Title Authors
11:00	10.2.1	LOGIC OPTIMIZATION AND SYNTHESIS: TRENDS AND DIRECTIONS IN INDUSTRY Speaker: Luca Amaru, Synopsys Inc., US Authors: Luca Amaru, Patrick Vuillod, Jiong Luo and Janet Olson, Synopsys, US Abstract Logic synthesis is a key design step which optimizes abstract circuit representations and links them to technology. With CMOS technology moving into the deep nanometer regime, logic synthesis needs to be aware of physical informations early in the flow. With the rise of enhanced functionality nanodevices, research on technology needs the help of logic synthesis to capture advantageous design opportunities. This paper deals with the syn- ergy between logic synthesis and technology, from an industrial perspective. First, we present new synthesis techniques which embed detailed physical informations at the core optimization engine. Experiments show improved Quality of Results (QoR) and better correlation between RTL synthesis and physical implemen- tation. Second, we discuss the application of these new synthesis techniques in the early assessment of emerging nanodevices with enhanced functionality. Finally, we argue that new synthesis methods can push further the progress of electronics, as we have reached a multiforking point of technology where choices are tougher than ever. Download Paper (PDF; Only available from the DATE venue WiFi)
11:22	10.2.2	CARBON NANOTUBES ENABLE MAJOR ENERGY EFFICIENCY BENEFITS FOR SUB-10NM DIGITAL SYSTEMS Speaker: Gage Hills, Stanford University, US Authors: Gage Hills1, Max Shulaker2, Chi-Shuen Lee3, Peter Debacker4, Marie Garcia Bardon5, Dmitry Yakimets5, Romain Ritzenthaler5, Iuliana Radu5, Francky Catthoor5, Praveen Raghavan6, Aaron Thean7, H.-S. Philip Wong3 and Subhasish Mitra3 1Department of Electrical Engineering, Stanford University, US; 2MIT, US; 3Stanford University, US; 4imec vzw, BE; 5IMEC, BE; 6imec, BE; 7NU Singapore, SG
11:45	10.2.3	WAVE PIPELINING FOR MAJORITY-BASED BEYOND-CMOS TECHNOLOGIES Speaker: Odysseas Zografos, imec, BE Authors: Odysseas Zografos1, Anton De Meester1, Eleonora Testa2, Mathias Soeken2, Pierre-Emmanuel Gaillardon3, Giovanni De Micheli4, Luca Amaru5, Praveen Raghavan6, Francky Catthoor1 and Rudy Lauwereins1 1IMEC, BE; 2EPFL, CH; 3University of Utah, US; 4École Polytechnique Fédérale de Lausanne (EPFL), CH; 5Synopsys, US; 6imec, BE Abstract The performance of some emerging nanotechnologies benefits from wave pipelining. The design of such circuits requires new models and algorithms. Thus we show how Majority-Inverter Graphs (MIG) can be used for this purpose and we extend the related optimization algorithms. The resulting designs have increased throughput, something that has traditionally been a weak point for the majority of non-charge-based technologies. We benchmark the algorithm on MIG netlists with three different technologies, Spin Wave Devices (SWD), Quantum-dot Cellular Automata (QCA), and NanoMagnetic Logic (NML). We find that the wave pipelined version of the netlists have an improvement in throughput over power of 23x, 13x, and 5x for SWD, QCA, and NML, respectively. In terms of throughput over area ratio, the improvement is 5x, 8x, and 3x, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
12:07	10.2.4	DESIGN AUTOMATION FOR QUANTUM ARCHITECTURES Speaker: Martin Roetteler, Microsoft Research, US Authors: Martin Roetteler, Krysta M. Svore, Dave Wecker and Nathan Wiebe, Microsoft, US Abstract We survey recent strides made towards building a software framework that is capable of compiling quantum algorithms from a high-level description down to physical gates that can be implemented on a fault-tolerant quantum computer. We discuss why compilation and design automation tools such as the ones in our framework are key for tackling the grand challenge of building a scalable quantum computer. We then describe specialized libraries that have been developed using the LIQUi|> programming language. This includes reversible circuits for arithmetic as well as new, truly quantum approaches that rely on quantum computer architectures that allow the probabilistic execution of gates, a model that can reduce time and space overheads in some cases. We highlight why these libraries are useful for the implementation of many quantum algorithms. Finally, we survey the tool REVS that facilitate resource efficient compilation of higher-level irreversible programs into lower-level reversible circuits while trying to optimize the memory footprint of the resulting reversible networks. This is motivated by the limited availability of qubits for the foreseeable future. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Garden Foyer Keynote Lecture session 11.0 in "Garden Foyer" 1320 - 1350 Lunch Break in the Garden Foyer On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.