Topic: D8 Networks-on-Chip

Architecture, modeling and design techniques for Networks-on-Chips; design methods for the on-chip interconnection network: topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for NoCs; physical design techniques and methodologies; integration of external interfaces/memory controllers with NoCs; cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; industrial applications of NoCs; design of NoCs based on alternative technologies such as photonics/optics, wireless, 3D stacking.

Chair: Federico Angiolini, iNoCs, CH, Contact

Co-Chair: Fabien Clermidy, CEA-LETI, FR, Contact

Members:

• Paul Ampadu, University of Rochester, US, Contact
• Luca Benini, Università di Bologna, IT, Contact
• Davide Bertozzi, University of Ferrara, IT, Contact
• Luca Carloni, Columbia University, US, Contact
• Érika Cota, UFRGS, BR, Contact
• Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
• Josè Flich, Universidad Politecnica de Valencia, ES, Contact
• Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
• Andreas Hansson, ARM Ltd, UK, Contact
• Shaahin Hessabi, Sharif University of Technology, IR, Contact
• Axel Jantsch, KTH, SE, Contact
• Jung Ho Ahn, Seoul National University, KR, Contact
• Hiroki Matsutani, Keio University, JP, Contact
• Steven Nowick, Columbia University, US, Contact
• Pascal VIVET, CEA-LETI, FR, Contact
• Sungjoo Yoo, POSTECH, KR, Contact