Topic: D15 Modeling and Design for Signal and Power Integrity

Modeling, characterization and analysis of on and off chip interconnects, and packaging; modeling, design, and characterization of Through Silicon Vias (TSV), 3D Interconnects, and interposer; wireless interconnects via capacitive/inductive coupling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; EMC issues in interconnects: electromagnetic emission, susceptibility and compatibility; chip-package co-design, modeling, and noise coupling issues in 3D IC and packages; high-speed channel and equalizer modeling, design, and measurement; macro-modeling, behavioral, and reduced order modeling.

Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

Co-Chair: Joungho Kim, KAIST, KR, Contact

Members:

• Luca Daniel, Massachusetts Institute of Technology, US, Contact
• sung kyu lim, georgia tech, US, Contact
• Dries Vande Ginste, University of Ghent, BE, Contact