Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Bayard

Chair:
Stefano Grivet-Talocia, Politecnico di Torino, IT

This session discusses state-of-the-art approaches for modelling and design optimization of signal and power distribution networks. Advancements are illustrated on power supply pads placement based on locality and temperature-dependent electromigration, on optimized GPU implementations for capacitance extraction, jitter charaterization via incoherent undersampling and coding-based crosstalk mitigation.

Time	Label	Presentation Title Authors
14:00	11.6.1	PLACEMENT OPTIMIZATION OF POWER SUPPLY PADS BASED ON LOCALITY Authors: Pingqiang Zhou, Vivek Mishra and Sachin Sapatnekar, University of Minnesota, Twin Cities, US Abstract
14:30	11.6.2	GPU-FRIENDLY FLOATING RANDOM WALK ALGORITHM FOR CAPACITANCE EXTRACTION OF VLSI INTERCONNECTS Authors: Kuangya Zhai, Wenjian Yu and Hao Zhuang, Tsinghua University, CN Abstract
15:00	11.6.3	(Best Paper Award Candidate) PERIODIC JITTER AND BOUNDED UNCORRELATED JITTER DECOMPOSITION OF INCOHERENT UNDERSAMPLING Authors: Nicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao and Abhijit Chatterjee, Georgia Tech, US Abstract
15:15	11.6.4	CROSSTALK AVOIDANCE CODES FOR 3D VLSI Speaker: Sachin Sapatnekar, University of Minnesota, US Authors: Rajeev Kumar and Sunil Khatri, Texas A&M University, US Abstract
15:30	IP5-17, 915	LARGE-SCALE FLIP-CHIP POWER GRID REDUCTION WITH GEOMETRIC TEMPLATES Author: Zhuo Feng, Michigan Technological University, US Abstract
15:30		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.