| D1 System Specification and Modeling | Chair Eugenio Villar
Universidad de Cantabria, ES
villar@teisa.unican.es
Co-Chair Grant Martin
Tensilica, USA
gmartin@tensilica.com
|
| D2 MPSoC and System Design Methods | Chair Luciano Lavagno
Cadence, US
luciano@cadence.com
Co-Chair Wido Kruijtzer
NXP Semiconductors, NL
wido.kruijtzer@nxp.com
|
| D3 System Synthesis and Optimization | Chair Peter Marwedel
University of Dortmund, DE
Peter.Marwedel@udo.edu
Co-Chair Paul Pop
Technical University of Denmark, DK
pop@imm.dtu.dk
|
| D4 Simulation and Validation | Chair Franco Fummi
University of Verona, IT
franco.fummi@univr.it
Co-Chair Ian Harris
University of California Irvine, USA
harris@ics.uci.edu
|
| D5 Design of Low Power Systems | Chair Miguel Miranda
IMEC, BE
miranda@imec.be
Co-Chair Alberto Macii
Politecnico di Torino, IT
alberto.macii@polito.it
|
| D6 Power Estimation and Optimization | Chair Joerg Henkel
University of Karlsruhe, DE
henkel@informatik.uni-karlsruhe.de
Co-Chair Kaushik Roy
Purdue University, USA
kaushik@ecn.purdue.edu
|
| D7 Emerging Technologies, Systems and Applications | Chair Sandeep Shukla
Virginia Tech, USA
shukla@vt.edu
Co-Chair Yuan Xie
Penn State University, USA
yuanxie@cse.psu.edu
|
| D8 Formal Methods and Verification | Chair Jason Baumgartner
IBM Corporation, Austin, TX, USA
jason.r.baumgartner@gmail.com
Co-Chair Joao Marques-Silva
University of Southampton, UK
jpms@ecs.soton.ac.uk
|
| D9 Network on Chip | Chair Axel Jantsch
KTH, SE
axel@imit.kth.se
Co-Chair Li-Shiuan Peh
Princeton University, USA
peh@Princeton.EDU
|
| D10 Architectural and Microarchitectural Design | Chair Dionisios Pnevmatikatos
Technical University of Crete, GR
pnevmati@ics.forth.gr
Co-Chair Christos Kozyrakis
Stanford University, USA
christos@ee.stanford.edu
|
