Date: Thursday 27 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 5

Chair:
Jose Monteiro, INESC-ID / Tecnico, ULisboa, PT

Co-Chair:
Elena Dubrova, Royal Institute of Technology, SE

The papers in this session present static timing techniques and tools for the analysis and synthesis of logic circuits. The papers take into account new aspects of timing analysis like variability, leakage and sign-off.

Time	Label	Presentation Title Authors
08:30	9.7.1	(Best Paper Award Candidate) FACILITATING TIMING DEBUG BY LOGIC PATH CORRESPONDENCE Speakers: Oshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer and Inna Grijnevitch, IBM, IL Abstract Synthesis tools for high-performance VLSI designs employ aggressive logic optimization techniques in order to meet physical requirements such as area and cycle time. During these optimizations, the original structure of the design, which is usually written in a hardware description language (HDL), is lost. It is difficult, and often impossible, to relate signals after synthesis to the original signals in the HDL code. Some signals only lose their names while for others there are no equivalent counterparts in the design after synthesis. Debugging timing problems is based on timing reports which are usually represented in terms of the post-synthesis design. Hence, it is difficult to relate critical paths in the timing reports to the relevant paths in the HDL code when a logic fix is needed. In this paper, we propose a different approach for dealing with the correspondence problem: instead of trying to relate signals we relate paths. Given a critical path in a post-synthesis representation, our method is able to find all corresponding paths in the pre-synthesis (HDL) representation. As a result, locating the parts in the HDL which are relevant to the given timing problem becomes trivial. A novel Sat-based algorithm for dealing with the path-correspondence problem is described. Experimental results on various industrial high-end processor designs show the effectiveness of our algorithm in substantially reducing the amount of paths in the HDL which one will have to consider when debugging a given critical path.
09:00	9.7.2	STATISTICAL STATIC TIMING ANALYSIS USING A SKEW-NORMAL CANONICAL DELAY MODEL Speakers: Vijaykumar M and V Vasudevan, Department of Electrical Engineering Indian Institute of Technology Madras, IN Abstract In its simplest form, a parameterized block based statistical static timing analysis (SSTA) is performed by assuming that both gate delays and the arrival times at various nodes are Gaussian random variables. These assumptions are not true in many cases. Quadratic models are used for more accurate analysis, but at the cost of increased computational complexity. In this paper, we propose a model based on skew-normal random variables. It can take into account the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. We derive analytical expressions for the moments of the MAX operator based on the conditional expectations. The computational complexity of using this model is marginally higher than the linear model based on Clark's approximations. The results obtained using this model match well with Monte-Carlo simulations.
09:30	9.7.3	LEAKAGE-POWER-AWARE CLOCK PERIOD MINIMIZATION Speakers: Hua-Hsin Yeh1, Shih-Hsu Huang1 and Yow-Tyng Nieh2 1Chung Yuan Christian University, TW; 2Industrial Technology Research Institute, TW Abstract In the design of nonzero clock skew circuits, an increase of the path delay may improve circuit speed and reduce leakage power. However, the impact of increasing path delay on the trade-off between circuit speed and leakage power has not been well studied. In this paper, we propose a two-step approach for leakage-power-aware clock period minimization. Compared with previous works, our approach has the following two significant contributions. First, our approach is the first leakage-power-aware clock skew scheduling that can guarantee working with the lower bound of the clock period. Second, our approach is also the first work that demonstrates the problem of minimizing the number of extra buffers is a polynomial-time problem. Benchmark data show that our approach achieves the best results in terms of the clock period and the leakage power.
09:45	9.7.4	A DEEP LEARNING METHODOLOGY TO PROLIFERATE GOLDEN SIGNOFF TIMING Speakers: Seung-Soo Han1, Andrew B. Kahng2, Siddhartha Nath2 and Ashok S. Vydyanathan2 1Myongji University, Yongin, KR; 2University of California, San Diego, US Abstract Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design methodologies, and implementation flows make timing closure very complex at advanced technology nodes. Reported timing slacks directly affect chip area and power by forcing additional buffering or sizing (negative slacks), or limiting area and power recovery (positive slacks). Design teams often wish to ensure that one tool's timing reports are neither optimistic nor pessimistic with respect to another tool's reports. The resulting "correlation" problem is highly complex because tools contain millions of lines of black-box and legacy code, licenses prevent any reverse-engineering of algorithms, and the nature of the problem is seemingly "unbounded" across possible designs, timing paths, and electrical parameters. In this work, we apply a "big-data" mindset to approach the timer correlation problem. We develop a machine learning-based tool, Golden Timer eXtension (GTX), to correct divergence in flip-flop setup time, cell arc delay, wire delay, stage delay, and path slack at timing endpoints between timers. Our models are developed with datasets of >300K data points for cell, wire, and stage delays and >30K data points for path slack and flip-flop setup time. We propose a methodology to apply GTX to two arbitrary timers, and we evaluate scalability of GTX across multiple designs and foundry technologies / libraries, both with and without signal integrity analysis. Our experimental results show reduction in divergence between timing tools from 139.3ps to 21.1ps (i.e., 6.6×) in endpoint slack, from 25.6ps to 2.4ps (i.e., 10× reduction) in flip-flop setup time, from 454.4ps to 51.9ps (i.e., 8.7× reduction) in cell delay, from 194.8ps to 17.4ps (i.e., 11.2× reduction) in wire delay, and from 117ps to 23.8ps (4.9× reduction) in stage delay. The average (mean) divergence in timing reports after applying GTX is almost zero. We further demonstrate the incremental application of our methods so that models can be adapted to any outlier discrepancies when new designs are taped out in the same technology / library. Last, we demonstrate that GTX can also correlate timing reports between signoff and design implementation tools.
10:00	IP4-17, 759	AGING-AWARE STANDARD CELL LIBRARY DESIGN Speakers: Saman Kiamehr1, Farshad Firouzi1, Mojtaba Ebrahimi2 and Mehdi Tahoori2 1Karlsruhe Institute of Technology (KIT), DE; 2Karlsruhe Institute of Technology, DE Abstract Transistor aging, mostly due to Bias Temperature Instability (BTI), is one of the major unreliability sources at nano-scale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, standard cells in the library are optimized according to the design time delay, however, due to the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this paper, the BTI effect is mitigated by balancing the rise and fall delays of the standard cells at the excepted lifetime. We find an optimal trade-off between the increase in the size of the library and the lifetime improvement (timing margin reduction) by non-uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that our technique can prolong the circuit lifetime by around 150% with a negligible area overhead.
10:01	IP4-18, 279	PASS-XNOR LOGIC: A NEW LOGIC STYLE FOR P-N JUNCTION BASED GRAPHENE CIRCUITS Speakers: Valerio Tenace, Andrea Calimera, Enrico Macii and Massimo Poncino, Politecnico di Torino, IT Abstract In this work we introduce a new logic style for p-n junctions based digital graphene circuits: the pass-XNOR logic style. The latter enables the realization of compact, energy efficient circuits that better exploit the characteristics of graphene. We first show how a single p-n junction can be conceived as a pass-XNOR gate, i.e., a transmission gate with embedded logic functionality, the XNOR Boolean operator. Secondly, we propose a smart integration strategy in which series/parallel connections of pass-XNOR gates allow to implement AND/OR logical conjunctions, and, therefore, all possible truth tables. Experimental results conducted on a set of representative logic functions show the superior of pass-XNOR logic circuits w.r.t. standard CMOS circuits and graphene circuits that use p-n junctions in a complementary-like structure.
10:02	IP4-19, 365	MIXED ALLOCATION OF ADJUSTABLE DELAY BUFFERS COMBINED WITH BUFFER SIZING IN CLOCK TREE SYNTHESIS OF MULTIPLE POWER MODE DESIGNS Speakers: Kitae Park, Geunho Kim and Taewhan Kim, Seoul National University, KR Abstract Recently, many works have shown that adjustable delay buffer (ADB) whose delay is adjustable dynamically can effectively solve the clock skew variation problem in the designs with multiple power modes. However, all the previous works of ADB allocation inherently entail two critical limitations, which are the adjusted delays by ADB are always increments and the low cost buffer sizing has never been or not been primarily taken into account. To demonstrate how much overcoming the two limitations is effective in resolving the clock skew constraint, we characterize the two types of ADBs called CADB (capacitor based ADB) and IADB (inverter based ADB) and show that the adjusted delays by IADB can be decremented, and show that the clock skew violation in some clock trees of multiple power modes can be resolved by applying buffer sizing together with using only a small number of IADBs and CADBs.
10:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).