Date: Thursday 27 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 3

Organisers:
Andreas Herkersdorf, Technische Universität München, Ge
Ulf Schlichtmann, Technische Universität München, Ge

Chair:
Nikil Dutt, University of California, Irvine, US

Co-Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software countermeasures is most effective. Interfaces such as the presented Resilience Articulation Point (RAP) or the Reliability Interchange Information Format (RIIF) are required to enable EDA-assisted analysis and propagation of reliability information. The models are discussed from different perspectives, such as design and test.

Time	Label	Presentation Title Authors
08:30	9.5.1	INTRODUCTION TO RAP (RESILIENCE ARTICULATION POINT) Speaker: Andreas Herkersdorf, TU München, DE
08:45	9.5.2	SYSTEM LEVEL DESIGN USING RAP (RESILIENCE ARTICULATION POINT) Speaker: Ulf Schlichtmann, Technische Universität München, DE Abstract We will demonstrate how technology characteristics can be included in system-level reliability analysis using the RAP (Resilience Articulation Point) model. The specific example of a two-wheeled robot will be used.
09:00	9.5.3	CROSS-LAYER RELIABILITY IN THE DESIGN OF AN ERROR RESILIENT COMMUNICATION SYSTEM Speaker: Norbert Wehn, University of Kaiserslautern, DE
09:15	9.5.4	RIIF - TOWARD A STANDARD APPROACH FOR CREATING RELIABILITY MODELS FOR COMPLEX SILICON DEVICES Speaker: Adrian Evans, IROC Technologies, FR Abstract Complex silicon devices are increasingly controlling critical systems where safety and reliability are key concerns. Silicon technology is subject to numerous failure modes which can be broadly classified into soft- error effects (due to natural radiation) and life-time effects (e.g. electro-migration, NBTI, HCI). It is necessary to consider all of these failure modes and how they propagate through the system and produce user-visible effects. There are no consistent tools or methodologies to address this problem. Current ad-hoc approaches are not able to cope with the diversity of technology failure modes, increased design sizes and the complex relationships between consumers and suppliers of electronic components. RIIF (Reliability Information Interchange Format), is an initiative to develop a standard modelling language for specifying the failure mechanisms in silicon devices and systems built using these devices. In this session we give a brief overview of RIIF and present an example that highlights some of the challenges in reliability modelling.
09:30	9.5.5	TEST PERSPECTIVES Speaker: Jacob Abraham, UT Austin, US
09:45	9.5.6	INDUSTRIAL PERSPECTIVE Speaker: Sani Nassif, IBM, US
10:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).