Date: Thursday 27 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 2

Chair:
Elena Ioana Vatajelu, Politecnico di Torino, IT

Co-Chair:
Mark Zwolinski, University of Southampton, UK

Accelerated timing simulation is essential for today's chip designs, whether it is performed at the gate-level or at the system-level. This session provides solutions to address the challenges of timing analysis and timing validation performance across multiple levels of design's abstractions.

Time	Label	Presentation Title Authors
08:30	9.4.1	FAST STA PREDICTION-BASED GATE-LEVEL TIMING SIMULATION Speakers: Tariq Bashir Ahmad and Maciej Ciesielski, UMASS Amherst, US Abstract Traditional dynamic simulation with standard delay format (SDF) back-annotation cannot be reliably performed on large designs. The large size of SDF files makes the event-driven timing simulation extremely slow as it has to process an excessive number of events. In order to accelerate gate-level timing simulation we propose an automated fast prediction-based gate-level timing simulation that combines static timing analysis (STA) at the block level with dynamic timing simulation at the I/O interfaces. We demonstrate that the proposed timing simulation can be done earlier in the design cycle in parallel with synthesis.
09:00	9.4.2	A CROSS-LEVEL VERIFICATION METHODOLOGY FOR DIGITAL IPS AUGMENTED WITH EMBEDDED TIMING MONITORS Speakers: Valerio Guarnieri1, Massimo Petricca2, Alessandro Sassone2, Sara Vinco1, Nicola Bombieri1, Franco Fummi3, Enrico Macii2 and Massimo Poncino2 1University of Verona, IT; 2Politecnico di Torino, IT; 3Universita' di Verona, IT Abstract Smart systems implement the leading technology advances in the context of embedded devices. Current design methodologies are not suitable to deal with tightly interacting subsystems of different technological domains, namely analog, digital, discrete and power devices, MEMS and power sources. The effects of interaction between components and with the environment must be modeled and simulated at system level to achieve high performance. Focusing on the digital domain, additional design constraints have to be considered as a result of the integration of multi-domain subsystems in a single device. The main digital design challenges, combined with those emerging from the heterogeneous nature of the whole system, directly impact on performance and on propagation delay of the digital component. This paper proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems, and a methodology to verify the added features at system-level. The design approach consists of augmenting the RTL model through the automatic insertion of delay sensors, which can detect and correct timing failures. The augmented model is abstracted to SystemC TLM and, then, mutants (i.e., code mutations for emulating timing failures) are automatically injected into the model. Experimental results demonstrate the applicability of the proposed design and verification methodology and the effectiveness of the simulation performance.
09:30	9.4.3	EMPOWERING STUDY OF DELAY BOUND TIGHTNESS WITH SIMULATED ANNEALING Speakers: Xueqian Zhao and Zhonghai Lu, KTH Royal Institute of Technology, SE Abstract Studying the delay bound tightness typically takes a practical approach by comparing simulated results against analytic results. However, this is often a manual process whereas many simulation parameters have to be configured before the simulations run. This is a tedious and time-consuming process. We propose a technique to automate this process by using a simulated annealing approach. We formulate the problem as an online optimization problem, and embed a simulated annealing algorithm in the simulation environment to guide the search of configuration parameters which give good tightness results. This is a fully automated procedure and thus provide a promising path to automatic design space exploration in similar contexts. Experiment results of an all-to-one communication network with large searching space and complicated constraints illustrate the effectiveness of our method.
10:00	IP4-15, 665	(Best Paper Award Candidate) ANALYSIS AND EVALUATION OF PER-FLOW DELAY BOUND FOR MULTIPLEXING MODELS Speakers: Yanchen Long1, Zhonghai Lu2 and Xiaolang Yan3 1Zhejiang University and KTH Royal Institute of Technology, SE; 2KTH Royal Institute of Technology, SE; 3Zhejiang University, CN Abstract Multiplexing models are common in resource sharing communication media such as buses, crossbars and networks. While sending packets over a multiplexing node, the packet delay bound can be computed using network calculus models. The tightness of such delay bound remains an open problem. This paper studies the multiplexing models for weighted round robin scheduling with different traffic arrival curves, and analyzes per-flow packet delay bounds with different service properties. We empirically evaluate the tightness of the delay bounds. Our results show the quality of different analysis models, and how influential each parameter is to tightness.
10:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).