Date: Wednesday 26 March 2014
Time: 17:00 - 18:30
Location / Room: Konferenz 5

Chair:
Robert Aitken, ARM, US

Co-Chair:
Mehdi Tahoori, KIT, DE

As technology dimensions shrink and process complexity increases, it becomes vital to accurately model performance limiters such as device and metal variability, as well as to determine when these effects become so critical that delay requirements are exceeded.

Time	Label	Presentation Title Authors
17:00	8.7.1	EFFICIENT PERFORMANCE ESTIMATION WITH VERY SMALL SAMPLE SIZE VIA PHYSICAL SUBSPACE PROJECTION AND MAXIMUM A POSTERIORI ESTIMATION Speakers: Li Yu1, Sharad Saxena2, Christopher Hess2, Ibrahim (Abe) Elfadel3, Dimitri Antoniadis4 and Duane Boning4 1Massachusetts Institute of Technology, US; 2PDF Solution, Inc, US; 3Masdar Institute of Science and Technology, AE; 4MIT, US Abstract In this paper, we propose a novel integrated circuits performance estimation algorithm through a physical subspace projection and maximum-a-posteriori (MAP) estimation. Our goal is to estimate the distribution of a target circuit performance with very small measurement samples from on-chip monitor circuits. The key idea in this work is to exploit the fact that simulation and measurement data are physically correlated under different circuit configurations and topologies. First, different groups of measurements are projected to a subspace spanned by a set of physical variables. The projection is achieved by performing a sensitivity analysis of measurement parameters with respect to the subspace variables using virtual source compact model. Then a Bayesian treatment is developed by introducing prior distributions over these subspace variables. Maximum a posteriori estimation is then applied using the prior, and an expectation-maximization (EM) algorithm is used to estimate the circuit performance. The proposed method is validated by post-silicon measurement for a commercial 28-nm process. An average error reduction of 2x is achieved which can be translated to 32x reduction on data needed for samples on the same die. A 150x and 70x sample size reduction on training dies is also achieved compared to traditional least-square fitting method and least-angle regression method respectively without reducing accuracy.
17:30	8.7.2	JOINT VIRTUAL PROBE: JOINT EXPLORATION OF MULTIPLE TEST ITEMS' SPATIAL PATTERNS FOR EFFICIENT SILICON CHARACTERIZATION AND TEST PREDICTION Speakers: Shuangyue Zhang1, Fan Lin2, Chun-Kai Hsu2, Kwang-Ting Cheng2 and Hong Wang1 1Department of Automation, Tsinghua University, CN; 2Department of Electrical and Computer Engineering, University of California, Santa Barbara, US Abstract Virtual Probe (VP), proposed for characterization of spatial variations and for test time reduction, can effectively reconstruct the spatial pattern of a test item for an entire wafer using measurement values from only a small fraction of dies on the wafer. However, VP calculates the spatial signature of each test item separately, one item at a time, resulting in very long runtime for complex chips which often require hundreds, or even thousands, of test items in production. In this paper, we propose a new method, named Joint Virtual Probe (JVP), which can jointly derive spatial patterns of multiple test items. By simultaneously handling a large group of test items, JVP significantly reduces the overall runtime. And the prediction accuracy can also be improved because of JVP's implicit use of inter-test-item correlations in predicting spatial patterns. The experimental results on two industrial products, with 277 and 985 parametric test items in the production test programs respectively, demonstrate that, JVP achieves an average speedup of ～170X and ～50X over VP in the pre-test analysis and the test application phases respectively, as well as a slightly higher prediction accuracy than VP.
18:00	8.7.3	SUBSTITUTING TRANSITION FAULTS WITH PATH DELAY FAULTS AS A BASIC DELAY FAULT MODEL Speaker: Irith Pomeranz, Purdue University, US Abstract Comparing a single transition fault with a single path delay fault, targeting (i.e., simulating or generating a test for) a path delay fault is not more complex than targeting a transition fault. However, targeting a set of path delay faults is significantly more complex than targeting a set of transition faults when the goal is to consider the testable path delay faults that are associated with the longest paths. The reason is the large fraction of untestable path delay faults among these faults. This complication is removed if the requirement on the lengths of the paths is removed. In this case, it is possible to use path delay faults instead of transition faults as a basic delay fault model for better coverage of small delay defects. This paper studies the effects of using path delay faults as a basic delay fault model instead of transition faults.
18:15	8.7.4	STANDARD CELL LIBRARY TUNING FOR VARIABILITY TOLERANT DESIGNS Speakers: Sebastien Fabrie1, Juan Diego Echeverri2, Maarten Vertregt2 and Jose Pineda2 1Eindhoven University of Technology, NL; 2NXP Semiconductors, NL Abstract In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.
18:30	IP4-11, 194	PROBABILISTIC STANDARD CELL MODELING CONSIDERING NON-GAUSSIAN PARAMETERS AND CORRELATIONS Speakers: André Lange1, Christoph Sohrmann1, Roland Jancke1, Joachim Haase1, Ingolf Lorenz2 and Ulf Schlichtmann3 1Fraunhofer Institute for Integrated Circuits (IIS), Design Automation Division (EAS), DE; 2GLOBALFOUNDRIES Inc., DE; 3Technische Universität München, DE Abstract Variability continues to pose challenges to integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions to particular problems exist, but they do not allow a common view on performance variability including potentially correlated and non-Gaussian parameter distributions. In this paper, we present a probabilistic approach for variability modeling as an alternative: model parameters are treated as multi-dimensional random variables. Such a fully multivariate statistical description formally accounts for correlations and non-Gaussian random components. Statistical characterization and model application are introduced for standard cells and gate-level digital circuits. Example analyses of circuitry in a 28 nm industrial technology illustrate the capabilities of our modeling approach.
18:30		End of session
19:30		DATE Party in "Gläserne Manufaktur" of the Volkswagen AG The DATE Party is again scheduled on the second conference day, Wednesday, March 26, 2014, starting from 19:30 h. This year, it will take place in one of Dresden's most exciting and modern buildings, the "Gläserne Manufaktur" of the car manufacturer Volkswagen AG (www.glaesernemanufaktur.de/en/). The party will feature a flying buffet style dinner with various catering points and accompanying drinks. Light background music and the possibility of guided visits through the extraordinary premises will round off the evening. It provides a perfect opportunity to meet friends and colleagues in a relaxed atmosphere while enjoying local amenities. Please kindly note that it is no seated dinner. All delegates, exhibitors and their guests are encouraged to attend the party. Please be aware that entrance is only possible with a party ticket. Each full conference registration includes a ticket for the DATE Party. Additional tickets can be purchased on-site at the registration desk (subject to availability of tickets). Ticket price for the full Evening Social Programme: 75 € per person.