Date: Wednesday 26 March 2014
Time: 11:00 - 12:30
Location / Room: Saal 1

Organiser:
Jörg Henkel, Karlsruhe Institute of Technology, DE

Chair:
Jörg Henkel, Karlsruhe Institute of Technology, DE

Co-Chair:
Jürgen Teich, University of Erlangen-Nuremberg, DE

Dark Silicon is predicted to dominate the chip footage of upcoming many-core systems within a decade since Dennard Scaling fails mainly due to the voltage-scaling problem that results in higher power densities. It would deem upcoming technologies nodes inefficient since a majority of cores would lie fallow. Significant research efforts have started within the last couple of years to investigate and mitigate Dark Silicon effects to ensure an effective use of available chip footage. This special session gives a snapshot of current research activities of this grand challenge. In particular, the three talks present the newest trends and developments starting with the problem of Dennard Scaling and how it mandates new design constraints followed by the problem of power delivery and cooling, and concluding with the newest directions in efficient resource management for many-core systems.

Time	Label	Presentation Title Authors
11:00	6.1.1	A LANDSCAPE OF THE NEW DARK SILICON DESIGN REGIME Speaker: Michael Taylor, University of California, San Diego, US Abstract Due to the breakdown of Dennard scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark silicon, i.e., significantly underclocked or idle for large periods of time. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that "spend" area to "buy" energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. This work examines four key approaches—the four horsemen—that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits. Further, we propose a set of dark silicon design principles, and examine how one of the darkest computing architectures of all, the human brain, trades off energy and area in ways that provide potential insights into future directions for computer architecture.
11:30	6.1.2	INTEGRATED MICROFLUIDIC POWER GENERATION AND COOLING FOR BRIGHT SILICON MPSOCS Speakers: Mohamed M. Sabry1, Arvind Sridhar1, Patrick Ruch2, David Atienza1 and Bruno Michel2 1EPFL, CH; 2IBM Research, CH Abstract The soaring demand for computing power in our digital information age has produced, as collateral undesirable effect, a surge in power consumption and heat density for Multiprocessors System-on-Chip (MPSoC). Accordingly, significant portion of the energy consumed in state-of-the-art MPSoCs is dissipated in cooling. The remaining energy is used for computation, and causes the temperature ramp-up to operating conditions that already preclude operating all the cores at maximum performance levels, in order to prevent system overheating and failures. This situation is set to worsen as shipments of high-end (i.e., even denser) many-core servers are increasing at a 25% compound annual growth rate. With more power demands, MPSoCs will face a power delivery wall due to the reliability limitations of the underlying power delivery medium. Thus, state-of-the-art worst-case power and cooling delivery solutions are reaching their limits and it will no longer be possible to power up simultaneously all the available on-chip cores (situation known as the existence of dark silicon); hence, drastically limiting the benefits of technology scaling. In this paper we propose a disruptive approach to overcome the prevailing worst-case power and cooling provisioning paradigm for MPSoCs. This proposed approach integrates MPSoC with an on-chip microfluidic fuel cell network for joint cooling delivery and power supply (i.e., local power generation and delivery). By providing an alternative mean to power delivery integrated with cooling, MPSoCs are expected to gain in IO connectivity. Thanks to this disruptive technology, we can envision the removal of the current limits of power delivery and heat dissipation in server designs, subsequently avoiding dark silicon in future MPSoCs and enabling new perspectives in future energy-proportional computing architecture designs.
12:00	6.1.3	EFFECTIVE RESOURCE MANAGEMENT TOWARDS EFFICIENT COMPUTING Speaker: Per Stenström, Chalmers University of Technology, SE Abstract Improving performance of computers at historical rates, as dictated by Moore's Law, is becoming increasingly more challenging especially because we are hitting the chip power-budget wall. But challenges usually direct us to focus on opportunities we have neglected in the past. I will focus on some of these overlooked opportunities in this talk. One such opportunity is to question what are meaningful performance goals for individual applications. I will present a resource management framework in which architectural resources are assigned to applications based on their performance requirements. I will also talk about some innovations that enable us to compute more power-efficiently by using memory resources more effectively by, for example, exploiting value locality.
12:30		End of session Lunch Break in Exhibition Area Sandwich lunch