Date: Wednesday 26 March 2014
Time: 08:30 - 10:00
Location / Room: Exhibition Theatre

Organisers:
Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE
Kai Hahn, University Siegen, DE

Chair:
Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE

Co-Chair:
Kai Hahn, University Siegen, DE

System Integration using 3D technology is a very promising way to cope with current and future requirements for electronic systems. Since the pure shrinking of devices (known as "More Moore") will come to an end due to physical and economic restrictions, the integration of systems (e.g. by stacking dies, or by adding sensor functions) shows a way to maintain the growth in complexity as well as in diversity which is necessary for future applications. This so called "More than Moore" approach complements the conventional SoC product engineering. This session gives insights in System Integration design challenges from different perspectives, ranging from design technology over MEMS product engineering and 3D interconnect to automotive cyber physical systems.

Time	Label	Presentation Title Authors
08:30	5.8.1	DESIGN TECHNOLOGY FOR 3-D INTEGRATED SYSTEMS Speaker: Andy Heinig, Fraunhofer IIS/EAS, DE Abstract More than Moore technologies (MtM) enable the dense integration of different circuits in a package. The short length and small spacing of wires enable high-speed and highly parallel interconnects between system parts as e.g. processor and memory. In the first part of the presentation we will give an overview on the current status of MtM from system-in-package up to 3D stacking with trough silicon vias at interposers or stacked directly. The second part of the presentation is dedicated to the design of MtM systems. One challenge is the tight integration of analog and digital dies that requests the consideration of several electrical and multi-physical interactions e.g. thermal management, power distribution and electromagnetic compatibility stronger than in 2D-SoC-design. The second challenge is the wide design space opened by MtM. It request new methods that guides the designer to find the best trade-off between system performance and production costs. By the means of Processor and WideIO memory integration at silicon interposer, that increases the memory bandwidth in future high-end applications we demonstrate new EDA methods for design space exploration, estimation of routing congestion and interposer routing.
08:45	5.8.2	SEMICONDUCTOR PACKAGING IS BACK TO EUROPE - ADVANCES IN SYSTEM INTEGRATION IN WAFER LEVEL PACKAGING Speaker: Steffen Kroehnert, NANIUM S.A. - Niederlassung Dresden, DE Abstract Different market segments from mobile communication and consumer to automotive see the increasing need to focus on system integration on less space instead of single components or functional groups. This drives advanced semiconductor packaging to diversify and become fairly more complex, but at the same time an integrated functional part of the system. The demand for more and more diversified functionality on same or even less space drives the development of "More-than-Moore" (MtM) solutions in the packaging world. The keyword is again "System-in-Package" (SiP). Chip-Package-Board Co-Design and Co-Development are essential key for success. Besides some theory, the paper will show some real product examples where system integration in the package saved up to 4X space on the board for the same functionality with even more performance. While today the majority of SiP is still realized using laminated organic substrate interposers, the need to close the gap to System-on-Chip (SoC) performance is driving closer distances of the single functional elements to each other. This can be realized by Fan-Out Wafer Level Packaging (FO-WLP) technologies, like eWLB (embedded Wafer Level Ball Grid Array), which overcomes Fan-In Wafer Level Packaging (FI-WLP) limitations especially in terms of system integration, keeping the advantages of scalability and cost efficient batch processing. In the paper the good progress made to develop eWLB as technology platform will be shown, mainly using FO-WLP as enabler for System-in-Package on Wafer Level (WLSiP).
09:00	5.8.3	MEMS AND 3D-IC PRODUCT ENGINEERING - TECHNOLOGY DESIGN FOR SYSTEM INTEGRATION Speaker: Kai Hahn, University Siegen, DE Abstract Taking into account the diversity of technologies from die manufacturing to packaging it becomes clear that for product engineering of integrated systems such as MEMS or stacked 3D circuits the constraints and inter-dependencies of design and manufacturing are of special interest. The configuration of these technologies is strongly application specific and design methods differ completely from the approach known from the development of conventional two dimensional ICs.The presentation will cover methods and tools for technology design in the area of MEMS as well as for 3D integration.
09:15	5.8.4	3D-TSV-HUB: POTENTIALS AND CHALLENGES FOR VERTICAL INTERCONNECTS IN NETWORKS-ON-CHIPS Speaker: Andreas Herkersdorf, TU München, DE Abstract Sophisticated Network-On-Chips (NoCs) will form the backbone for on-chip communication in future System-On-Chip designs. Already in conventional planar systems the synthesis of application specific NoCs is a complex task. When shifting to a stacked die environment, further degrees of freedom are added and a large design space is created. Through Silicon Vias (TSVs) are deployed for building vertical NoC links in a 3D systems. However, TSVs are cost intensive under several aspects. Area consumption is high due to large TSV diameters (compared to planar metal layer interconnect) and keep out areas in intermediate die layers. Furthermore, mechanical induced stress can lead to runtime failures and an overall low system yield. Therefore, in order to ensure that a minimum number of TSVs are performance and cost efficiently operated to their full capacity, a 3D-TSV-Hub has been proposed to support smart mapping of communication flows onto TSVs during NoC synthesis. Mechanisms to handle production and runtime failures are integrated into the 3D-TSV-Hub concept and also considered during synthesis. Design aspects like compliance to thermal requirements and manufacturing process requirements influence the optimization of 3D-NoCs. In order to consider such factors, we operate the NoC synthesis tool in interplay with Design Space Exploration and 3D-Floorplanner tools of project partners.
09:30	5.8.5	SENSORS AND POWER DRIVERS, BRIDGE BETWEEN SYSTEM ENVIRONMENT AND COMPUTING Speaker: Jochen Reisinger, Infineon Technologies Austria AG, AT Abstract There are many main drivers enabling the most significant innovations in system solutions which are based on, or only supported by, electronics. No doubt, the best known driver is the availability of deep submicron technology nodes for the implementation of computing functions (More Moore). But competitive system architectures and functional system partitionings (technology selections) strongly depend on highly efficient interfaces to the system environment. Those interfaces are supporting many functions as for example: a) The sensing of physical parameters (temperature, pressure, speed, power, ...) b) Providing power and control signals for actuators (drivers for motors, pumps, ...) c) Providing power for the computing system (- including safety, power up/down) d) Interfacing to human bodies and/or other system elements and e) Communication of system operative and control data (WiFi, Bluetooth, ..). Those interfaces ask for highly efficient (in terms of space, power, performance, .., and cost) 3D integration technologies and design methodologies. Infineon examples for sensors and drivers will be presented.
09:45	5.8.6	CONCLUSIONS AND DISCUSSION Speaker: Manfred Dietrich, Fraunhofer, DE
10:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).