Date: Wednesday 26 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 5

Chair:
Xiaoqing Wen, Kyushu Institute of Technology, JP

Co-Chair:
Grzegorz Mrugalski, Mentor Graphics, PL

The session covers generation of tests for different fault models including interconnect opens, interconnect for 3D memories, and small delay faults. Additionally test optimization for SoC designs is presented.

Time	Label	Presentation Title Authors
08:30	5.7.1	(Best Paper Award Candidate) EFFICIENT SMT-BASED ATPG FOR INTERCONNECT OPEN DEFECTS Speakers: Dominik Erb1, Karsten Scheibler1, Matthias Sauer2 and Bernd Becker2 1University of Freiburg, Chair of Computer Architecture, DE; 2University of Freiburg, DE Abstract Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations. It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values. Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude.
09:00	5.7.2	INTERCONNECT TEST FOR 3D STACKED MEMORY-ON-LOGIC Speakers: Mottaqiallah Taouil1, Mahmoud Masadeh1, Said Hamdioui1 and Erik Jan Marinissen2 1Delft University of Technology, NL; 2IMEC, BE Abstract Three-dimensional stacked IC (3D-SIC) technology based on Through-Silicon Vias (TSVs) provides numerous advantages as compared to traditional 2D-ICs. A potential application is memory stacked on logic, providing enhanced throughput, and reduced latency and power consumption. However, testing the TSV interconnects between the two dies is challenging, as both the memory and the logic die might come from different manufacturers. Currently, no standard exists and the proposed solutions fail to address dynamic and time-critical faults (at speed testing). In addition, memory vendors have not been in favor to put additional DfT structures such as JTAG for interconnect testing on their memory devices. This paper proposes a new Memory Based Interconnect Test (MBIT) approach for 3D stacked memories. Our test patterns are applied by read and write instructions to the memory and are validated by a case study where a 3D memory is assumed to be stacked on a MIPS64 processor. The main benefits of the MBIT approach are: (1) zero area overhead, (2) the ability to detect both static and dynamic faults and perform at speed testing, (3) flexibility in applying any test pattern, as this can be executed by the CPU on the logic die and (4) extreme short test execution time.
09:30	5.7.3	AN EFFECTIVE APPROACH TO AUTOMATIC FUNCTIONAL PROCESSOR TEST GENERATION FOR SMALL-DELAY FAULTS Speakers: Andreas Riefert1, Lyl Ciganda2, Matthias Sauer1, Paolo Bernardi2, Matteo Sonza Reorda3 and Bernd Becker1 1University of Freiburg, DE; 2Politecnico di Torino, IT; 3Politecnico di Torino - DAUIN, IT Abstract Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.
09:45	5.7.4	MULTI-SITE TEST OPTIMIZATION FOR MULTI-VDD SOCS USING SPACE- AND TIME-DIVISION MULTIPLEXING Speakers: Fotios Vartziotis1, Chrysovalantis Kavousianos2, Krishnendu Chakrabarty3, Rubin Parekhji4 and Arvind Jain4 1University of Ioannina, GR; 2Department of Computer Science and Engineering, University of Ioannina, GR; 3Duke University, US; 4Texas Instruments, IN Abstract Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly increasing the effectiveness of multi-site testing. However, TDM suffers from some inherent limitations that do not allow the fullest possible exploitation of TAM bandwidth. To overcome these limitations, we propose space-division multiplexing (SDM), which complements TDM and offers higher multi-site test efficiency. We implement space- and time-division multiplexing (STDM) using a new, scalable test-time minimization method based on a combination of bin packing and simulated annealing. Results for industrial SoCs, highlight the advantages of the proposed optimization method.
10:00	IP2-20, 50	AN EFFICIENT TEMPERATURE-GRADIENT BASED BURN-IN TECHNIQUE FOR 3D STACKED ICS Speakers: Nima Aghaee, Zebo Peng and Petru Eles, Linköping University, SE Abstract Burn-in is usually carried out with high temperature and elevated voltage. Since some of the early-life failures depend not only on high temperature but also on temperature gradients, simply raising up the temperature of an IC is not sufficient to detect them. This is especially true for 3D stacked ICs, since they have usually very large temperature gradients. The efficient detection of these early-life failures requires that specific temperature gradients are enforced as a part of the burn-in process. This paper presents an efficient method to do so by applying high power stimuli to the cores of the IC under burn-in through the test access mechanism. Therefore, no external heating equipment is required. The scheduling of the heating and cooling intervals to achieve the required temperature gradients is based on thermal simulations and is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed method.
10:01	IP2-21, 17	TEST AND NON-TEST CUBES FOR DIAGNOSTIC TEST GENERATION BASED ON MERGING OF TEST CUBES Speaker: Irith Pomeranz, Purdue University, US Abstract Test generation by merging of test cubes supports test compaction and test data compression. This paper describes a new approach to the use of test cube merging for the generation of compact diagnostic test sets. For this the paper uses the new concept of non-test cubes. While a test cube for a fault fi0 detects the fault, a non-test cube for a fault fi1 prevents the fault from being detected. Merging a test cube for a fault fi0 and a non-test cube for a fault fi1 produces a diagnostic test cube that distinguishes the two faults. The paper describes a procedure for diagnostic test generation based on merging of test and non-test cubes. Experimental results demonstrate that compact diagnostic test sets are obtained.
10:02	IP2-22, 905	NEW IMPLEMENTIONS OF PREDICTIVE ALTERNATE ANALOG/RF TEST WITH AUGMENTED MODEL REDUNDANCY Speakers: Haithem Ayari, Florence Azais, Serge Bernard, Mariane Comte, Vincent Kerzerho and Michel Renovell, LIRMM, CNRS/Univ. Montpellier 2, FR Abstract This paper discusses new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. This redundancy is then used during the testing phase to identify suspect predictions and remove the corresponding devices from the alternate test flow. In this paper, we explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set. The proposed implementations are evaluated on a real case study for which we have production test data from 10,000 devices.
10:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).