Date: Tuesday 25 March 2014
Time: 17:00 - 18:30
Location / Room: Konferenz 6

Organisers:
Jürgen Becker, KIT, DE
Oliver Sander, KIT, DE

Chair:
Jürgen Becker, KIT, DE

Co-Chair:
Oliver Sander, KIT, DE

Future applications in automotive and avionics show an ever increasing demand of computational processing power. The use of multicore devices is now emerging in embedded electronics. However these solutions are not directly applicable because of technical requirements that come along with the domain of safety critical and mixed critical applications, such as in automotive or avionics. The major challenge for deployment of multicore devices in safety critical applications such as automotive or avionics, is the lack of determinism and support of segregation due to shared resources. The goal of this session is to present the challenges that arise from the use of multicore devices in embedded safety-critical systems and mixed critical systems.

Time	Label	Presentation Title Authors
17:00	4.2.1	AUTOSAR AND MULTICORE Speakers: Stefan Kuntz1 and Rolf Schneider2 1Continental Automotive GmbH, DE; 2AUDI AG, DE Abstract AUTOSAR already supports developing applications for and integrating software components onto multicore based platforms. In addition, these capabilities pave the way for helping to migrate existing applications, originally developed for being executed on single core platforms, to multicore based platforms. This talk provides a brief introduction of the current state of AUTOSAR's multicore support and presents some scenarios that draws the attention to multicore specific questions and challenges in the particular context. Possible future directions in improving the AUTOSAR standard with regard to multicore and to gain more benefit from the availability of multiple cores, independent execution units, are sketched out.
17:30	4.2.2	CONCEPTS TO VALIDATE THE SAFE APPLICATION OF MULTICORE ARCHITECTURES IN THE AVIONICS DOMAIN Speaker: Ottmar Bender, Airbus Defence and Space, DE Abstract This presentation explains how commercially available multicore processors can be applied for safety critical applications in avionics systems. It also describes remaining difficulties which need to be solved for a full exploitation of multicore technology in the avionics domain. Furthermore a concept of an airborne radar application demonstrator built on multicore architecture is shown. This demonstrator shall allow the validation of essential solutions for the specific difficulties emerging from current multicore architectures.
18:00	4.2.3	MONITORING AND WCET ANALYSIS IN COTS MULTI-CORE-SOC-BASED MIXED-CRITICALITY SYSTEMS Speakers: Jan Nowotsch1, Michael Paulitsch2, Arne Henrichsen3, Werner Pongratz3 and Andreas Schacht3 1EADS Innovation Works, DE; 2EADS Innovation Work, DE; 3Cassidian, DE Abstract The performance and power efficiency of multi-core processors are attractive features for safety-critical applications, for example in avionics. But the inherent use of shared resources complicates timing analysability. In this paper we discuss a novel approach to compute the Worst-Case Execution Time (WCET) of multiple hard real-time applications scheduled on a Commercial Off-The-Shelf (COTS) multi-core processor. The analysis is closely coupled with mechanisms for temporal partitioning as, for instance, required in ARINC 653-based systems. Based on a discussion of the challenges for temporal partitioning and timing analysis in multi-core systems, we deduce a generic architecture model. Considering the requirements for re-usability and incremental development and certification, we use this model to describe our integrated analysis approach.
18:15	4.2.4	HARDWARE VIRTUALIZATION SUPPORT FOR SHARED RESOURCES IN MIXED-CRITICALITY MULTICORE SYSTEMS Speakers: Oliver Sander1, Timo Sandmann2, Viet Vu Duy3, Steffen Bähr3, Falco Bapp3, Juergen Becker3, Hans Ulrich Michel4, Dirk Kaule4, Daniel Adam4, Enno Luebbers5, Jürgen Hairbucher5, Andre Richter6, Christian Herber7 and Andreas Herkersdorf8 1KIT, DE; 2Karlsruhe Institute of Technology (KIT), DE; 3Karlsruhe Institute of Technology, DE; 4BMW F+T, DE; 5Intel GmbH, DE; 6TUM, DE; 7Technische Universität München, DE; 8TU München, DE Abstract Electric/Electronic architectures in modern automobiles evolve towards an hierachical approach where functionalities from several ECUs are consolidated into few domain computers. Performance requirements directly lead to multicore solutions but also to a combination of very different requirements on such ECUs. Using virtualization in addition is one promising way of achieving segregation in time and space of shared resources. Based on examples taken from the automotive domain several concepts for efficient hardware extensions of coprocessors and I/O devices are shown in this contribution. These provide mechanisms to ensure quality of service (QoS) levels in terms of exectution time, throughput and latency. The resulting infotainment architecture is a feasibility study and is integrated into a vehicle demonstrator as centralized infotainment platform (VCT).
18:30		End of session Exhibition Reception in Several serving points inside the Exhibition Area (Terrace Level) The Exhibition Reception will take place in the exhibition area (Terrace Level). All exhibitors are welcome to provide drinks and snacks for delegates and visitors.