Date: Tuesday 25 March 2014
Time: 14:30 - 16:00
Location / Room: Konferenz 2

Chair:
Luca Daniel, MIT, US

Co-Chair:
Stefano Grivet-Talocia, Politecnico di Torino, IT

The performance and robustness of 3D power distribution networks is of critical importance for state of the art electronic designs. The papers in this session discuss new modeling and optimization approaches for their efficient characterization and robust design, including order reduction, variability impact, via planning, decoupling capacitor selection, and thermal effects.

Time	Label	Presentation Title Authors
14:30	3.4.1	(Best Paper Award Candidate) SENSITIVITY-BASED WEIGHTING FOR PASSIVITY ENFORCEMENT OF LINEAR MACROMODELS IN POWER INTEGRITY APPLICATIONS Speakers: Andrea Ubolli1, Stefano Grivet-Talocia1, Michelangelo Bandinu2 and Alessandro Chinea2 1Politecnico di Torino, IT; 2IdemWorks s.r.l., IT Abstract The electrical performance of Power Distribution Networks (PDNs) is usually assessed by computing frequency responses through quasi-static or full-wave electromagnetic solvers. Such responses, often available in the scattering form, are then fed to suitable macromodeling algorithms for the extraction of compact reduced-order behavioral models that can be seemlessly simulated in the time domain by standard circuit solvers. Such algorithms perform a rational fitting of the raw scattering responses, followed by a passivity check and enforcement step. The resulting macromodel is typically very accurate when compared to the raw scattering responses. It may however happen that the responses of the PDN macromodel exhibit significant deviation from the true system responses under realistic loading conditions, which include appropriate models for active device blocks, decoupling capacitors, voltage regulators, etc. We highlight the source of this accuracy loss, and we propose a sensitivity-based weighting strategy that is able to optimize and tune the macromodel accuracy based on its specific nominal termination network. The particular focus of this paper is the definition and the inclusion of optimal weigths in the passivity enforcement step, which is recognized as the most challenging step. The result is a reliable macromodeling flow, which is able to produce passive, accurate and efficient reduced-order models of general PDN structures for power integrity analysis and verification.
15:00	3.4.2	EFFICIENT ANALYSIS OF VARIABILITY IMPACT ON INTERCONNECT LINES AND RESISTOR NETWORKS Speakers: Jorge Fernandez Villena1 and Luis Miguel Silveira2 1INESC ID, PT; 2INESC ID/IST - Lisbon University, PT Abstract Continued technology scaling coupled with limited lithographic capabilities is a leading cause of increased design variability. In the nanometer regime lithography tools have failed to keep pace with Moore's Law and printed feature sizes are a small fraction of the wavelength of light used in current processes. Such sub-wavelength printing makes features highly susceptible to perturbations in the lithographic process conditions which leads to printed designs exhibiting increased variability. Such variability directly affects design behavior and performance in multiple ways. One of the areas of concern is power grid (PG) design, where lithographic errors may locally modify the wire widths. These variations, that may affect any and all wires in the grid, have a critical impact on the power distribution across the chip, introducing considerable current fluctuations which are a potential cause for electromigration effects. To analyze and account for the impact of these errors requires a complete extraction of the PG, which generates a large resistive network, potentially with several million elements, whose simulation is computationally challenging. This paper proposes a fast and accurate variability analysis of very large resistor networks, such as PG extracted netlists, that allows estimating the effects of multiple parameter settings in reasonable time. The proposed model can be easily combined with Litho/CMP simulators in order to boost much needed design-aware lithography.
15:30	3.4.3	IMPLICIT INDEX-AWARE MODEL ORDER REDUCTION FOR RLC/RC NETWORKS Speakers: Nicodemus Banagaaya1, Giuseppe Ali'2, Wil . H. A. Schilders1 and Caren Tischendorf3 1Eindhoven University of Technology, NL; 2University of Calabria and INFN, Gruppo collegato di Cosenza, IT; 3Institute of Mathematics, Humboldt-Universit¨at zu Berlin, DE Abstract This paper introduces the implicit-IMOR method for differential algebraic equations. This method is a modification of the Index-aware model order reduction (IMOR) method proposed in our earlier papers which is the explicit-IMOR method. It also involves first splitting the differential-algebraic equations (DAEs) into differential and algebraic parts using a basis of projectors. In contrast with the explicit-IMOR method, the implicit-IMOR method leads to implicit differential and algebraic parts. We demonstrate the implicit-IMOR method using the RLC/RC networks, but it can also be applied to other problems which lead to differential-algebraic equations.
15:45	3.4.4	P/G TSV PLANNING FOR IR-DROP REDUCTION IN 3D-ICS Speakers: Shengcheng Wang1, Farshad Firouzi2, Fabian Oboril1 and Mehdi Tahoori1 1Karlsruhe Institute of Technology, DE; 2Karlsruhe Institute of Technology (KIT), DE Abstract In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated- Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D- ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design due to the increasing power density and larger supply current compared to 2D-ICs. As an important part of 3D-IC PDNs, Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be well-managed. Excessive or ill-placed P/G TSVs impact the power integrity (e.g. IR-drop), and also consume a considerable amount of chip real estate. In this work, we propose a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the P/G TSVs. The goal of our approach is to minimize the average IR-drop while satisfying the total area constraint of TSVs by optimizing the P/G TSV placement. Therefore, the locations, sizes and the total number of the P/G TSVs are co-optimized simultaneously. The experimental results show that the average IR-drop can be reduced by 11.8% in average using the proposed method compared to a random placement technique with a much smaller runtime.
16:00	IP1-15, 69	PACKAGE GEOMETRIC AWARE THERMAL ANALYSIS BY INFRARED-RADIATION THERMAL IMAGES Speakers: Jui-Hung Chien1, Hao Yu2, Ruei-Siang Hsu3, Hsueh-Ju Lin3 and Shih-Chieh Chang3 1Industrial Technology Research Institute, TW; 2None, TW; 3NTHU, TW Abstract Since packages affect the amount of heat transfer, it is important to include package and heat sink in thermal analysis. In this paper, we study the full-chip thermal response with different packages. We first discuss the difficulties of obtaining accurate package models for simulation. To facilitate a designer to perform thermal simulation with different packages, we propose to use a matrix called the package-transfer matrix which can transform a temperature profile of one package to another temperature profile of the desired package. To estimate and verify a package-transfer matrix, we propose an efficient method which uses Infrared Radiation (IR) images from two carefully design test chips with PBGA packages. Our experimental results show that the default package model CBGA in HotSpot can be accurately transferred to any other package through the package-transfer matrix.
16:01	IP1-16, 252	COST-EFFECTIVE DECAP SELECTION FOR BEYOND DIE POWER INTEGRITY Speakers: Yi-En Chen1, Tu-Hsung Tsai1, Shi-Hao Chen2 and Hung-Ming Chen1 1Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan 300, R.O.C., TW; 2Global Unichip Corp, Hsinchu, Taiwan, TW Abstract In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficientmethodology "PDCPSO" to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.
16:02	IP1-17, 554	CHARACTERIZING POWER DELIVERY SYSTEMS WITH ON/OFF-CHIP VOLTAGE REGULATORS FOR MANY-CORE PROCESSORS Speakers: Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu and Zhehui Wang, HKUST, HK Abstract Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fast voltage scaling and multiple power domains. Previous works are proposed to implement power efficient on-chip regulators. It is also important to analyze the characteristics of the entire power delivery system to explore the tradeoff between the promising properties and costs of employing on-chip regulators. In this work, we develop an analytical model to evaluate important characteristics of the power delivery system, including on-chip/off-chip voltage regulators and the passive on-chip/on-board parasitic. Compared with SPICE simulations, our model achieves a fast system-level evaluation with comparable accuracy. Based on the model, geometric programming is utilized to find the optimal power efficiency of different architectures of power delivery systems under constraints of output voltage stability and area. Experiments show that compared with the conventional architecture using off-chip regulators, the hybrid one using both on-chip and off-chip voltage regulators achieves 1.0% power efficiency improvement and 68% area reduction of voltage regulators on average. We conclude that the hybrid architecture has potential for high power efficiency and small area at heavy workload, but careful account for the overhead of on-chip regulators is needed.
16:03	IP1-18, 527	MASK-COST-AWARE ECO ROUTING Speakers: Hsi-An Chien1, Zhen-Yu Peng1, Yun-Ru Wu2, Ting-Hsiung Wang2, Hsin-Chang Lin2, Chi-Feng Wu2 and Ting-Chi Wang1 1National Tsing Hua University, TW; 2Realtek Semiconductor Corp., TW Abstract In this paper, we study a mask-cost-aware routing problem for engineering change order (ECO). By taking into account old routes for possible reuse, we present an approach for the problem. Encouraging experimental results are reported to demonstrate the effectiveness of our approach.
16:00		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).