Date: Tuesday 25 March 2014
Time: 11:30 - 13:00
Location / Room: Saal 1

Organiser:
Yervant Zorian, Fellow & Chief Architect, Synopsys, US

Executives:
Sanjive Agarwala, Fellow & Silicon Director, Texas Instruments, US
Paul Lo, Senior Vice President, Synopsys, US
Rainer Kress, Head Design Methodology, Infineon, DE
Wolfgang Maier, Director, IBM, DE

The widening gap between growing SOC complexity and designer productivity limits traditional chip design methods and flows. This results in several new approaches and innovative methods that work to elevate the limitations of different aspects of complex SOC design. Executives in this session will discuss the impact of complexity and the new opportunities it may bring in designing today's SOC.

Time	Label	Presentation Title Authors
13:00		End of session Lunch Break in Exhibition Area Sandwich lunch