Date: Thursday 27 March 2014
Time: 16:00 - 17:30
Location / Room: Konferenz 2

Chair:
Carl Sechen, University of Texas at Dallas, US

Co-Chair:
Jens Lienig, Technische Universität Dresden, DE

This session focuses on contemporary issues in physical design. The first paper concerns detailed placement for sub-20nm technologies. Then pattern matching for more efficient hotspot detection is introduced. Finally, a flow for minimizing the number of wiring layers on multichip interposers is presented.

Time	Label	Presentation Title Authors
16:00	12.4.1	OPTIMIZATION OF STANDARD CELL BASED DETAILED PLACEMENT FOR 16 NM FINFET PROCESS Speakers: Yuelin Du and Martin D. F. Wong, University of Illinois at Urbana-Champaign, US Abstract FinFET transistors have great advantages over traditional planner MOSFET transistors in high performance and low power applications. Major foundries are adopting the FinFET technology for CMOS semiconductor device fabrication in the 16 nm technology node and beyond. Edge device degradation is among the major challenges for the FinFET process. To avoid such degradation, dummy gates are needed on device edges, and the dummy gates have to be tied to power rails in order not to introduce unconnected parasitic transistors. This requires that each dummy gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which costs more placement area. Usually there is some flexibility during detailed placement to horizontally flip the cells or switch the positions of adjacent cells, which has little impact on the global placement objectives, such as timing conditions and net congestion. This paper proposes a detailed placement optimization strategy for the standard cell based designs. By flipping a subset of cells in a standard cell row and switching pairs of adjacent cells, the number of drain to drain abutments between adjacent cell boundaries can be optimally minimized, which saves additional source node insertion and reduces the length of the standard cell row. In addition, the proposed graph model can be easily modified to consider more complicated design rules. The experimental results show that the optimization of 100k cells is completed within 0.1 second, verifying the efficiency of the proposed algorithm.
16:30	12.4.2	SIGNATURE INDEXING OF DESIGN LAYOUTS FOR HOTSPOT DETECTION Speakers: Cristian Andrades1, Andrea Rodriguez1 and Charles Chiang2 1Universidad de Concepcion, CL; 2Synopsys Inc., US Abstract This work presents a new signature for 2D spatial configurations that is useful for the optimization of a hotspot detection process. The signature is a string of numbers representing changes along the horizontal and vertical slices of a configuration, which serves as the key of an inverted index that groups layout' windows with the same signature. The method extracts signatures from a compact specification of similar exact patterns with a fixed size. Then, these signatures are used as search keys of the inverted index to retrieve candidate windows that can match the patterns. Experimental results show that this simple type of signature has 100% recall and, in average, over 85% of precision in terms of the area effectively covered by the pattern and the retrieved area of the layout. In addition, the signature shows a good discriminate quality, since around 99% of the extracted signatures match each of them with a single pattern.
17:00	12.4.3	METAL LAYER PLANNING FOR SILICON INTERPOSERS WITH CONSIDERATION OF ROUTABILITY AND MANUFACTURING COST Speakers: Wen-Hao Liu, Tzu-Kai Chien and Ting-Chi Wang, National Tsing Hua University, TW Abstract A 2.5D IC provides a silicon interposer to integrate multiple dies into a package, which not only offers better performance than 2D ICs but also has lower manufacturing complexity than true 3D ICs. In an interposer, routing wires connect signals between dies or route signals from dies to the package substrate. The number of metal layers in an interposer is one of the critical factors to affect the routability and manufacturing cost of the 2.5D IC. Thus, how to achieve 100% routing completion rate in an interposer using a minimum number of metal layers plays a key role for the success of a 2.5D IC. This paper presents a global-routing-based metal layer planner called VGR to identify a minimal number of metal layers for an interposer with consideration of routability and manufacturing cost. Also, VGR can identify a good stacking order of the horizontal and vertical layers in an interposer such that the routing solution in the interposer costs fewer vias. To our best knowledge, this paper is the first study to solve the metal layer planning problem for silicon interposers.
17:30		End of session