Date: Thursday 27 March 2014
Time: 14:00 - 15:30
Location / Room: Konferenz 2

Chair:
Ronny Morad, IBM, IL

Co-Chair:
Franco Fummi, Universita' di Verona, IT

Fast platforms, whether acceleration, post-silicon or virtual prototypes, are key technologies to enabling validation of complex systems. However, they present enormous challenges to become effective. This session presents four papers and two IPs that propose solutions to overcome some of them, thus enabling much higher performance and coverage.

Time	Label	Presentation Title Authors
14:00	11.4.1	(Best Paper Award Candidate) COVERAGE EVALUATION OF POST-SILICON VALIDATION TESTS WITH VIRTUAL PROTOTYPES Speakers: Kai Cong, Li Lei, Zhenkun Yang and Fei Xie, Portland State University, US Abstract High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.
14:30	11.4.2	ARCHIVED: ARCHITECTURAL CHECKING VIA EVENT DIGESTS FOR HIGH PERFORMANCE VALIDATION Speakers: Chang-Hong Hsu1, Debapriya Chatterjee2, Ronny Morad3, Raviv Gal3 and Valeria Bertacco1 1University of Michigan, Ann Arbor, US; 2IBM Research - Austin, US; 3IBM Research - Haifa, IL Abstract Simulation-based techniques play a key role in validating the functional correctness of microprocessor designs. A common approach for validating microprocessors (called instruction-by-instruction, or IBI checking) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each instruction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI checking methodology. Indeed, validation on these platforms requires logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach following this paradigm entails a large slowdown for the acceleration platform, because of the sizable amount of data that must be transferred off-platform for comparison against the golden model. In this work we propose a sequence-by-sequence (SBS) checking approach that is efficient and practical for acceleration platforms. Our solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by more than 90%.
15:00	11.4.3	EFFECTIVE POST-SILICON FAILURE LOCALIZATION USING DYNAMIC PROGRAM SLICING Speakers: Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir and Vitali Sokhin, IBM Research - Haifa, IL Abstract In post-silicon functional validation, one of the complex and time-consuming processes is the localization of an instruction that exposes a bug detected at system level. The task is especially hard due to the silicon's limited observability and the long time between the failure's occurrence and its detection. We propose a novel method that automates the architectural localization of post-silicon test-case failures. The proposed tool analyzes a failing test-case, while leveraging the information derived from executing the test on an Instruction Set software Simulatior (ISS), to identify a set of instructions that could lead to the faulty final state. The proposed failure localization process comprises the creation of a resource dependency graph based on the execution of the test-case on the ISS, determining a program slice of instructions that influence the faulty resources, and the reduction of the set of suspicious instructions by leveraging the knowledge of the correct resources. We evaluate our proposed solution through extensive experiments. Experimental results show that, in over 97% of all cases, our method was able to narrow down the list of suspicious instructions to under 2 instructions, on average, out of over 200. In over 59% of all cases, our method correctly reduced a test-case to a single faulty instruction.
15:15	11.4.4	DESIGN-FOR-DEBUG ROUTING FOR FIB PROBING Speakers: Chia-Yi Lee, Tai-Hung Li and Tai-Chen Chen, National Central University, TW Abstract To observe internal signals, physical probing is an important step in post-silicon debug. Focused ion beam (FIB) is one of most popular probing technologies. However, an unsuitable layout significantly decreases the percentage of nets which can be observed through FIB probing for advanced process technologies. This paper presents the first design-for-debug routing to increase the FIB observable rate. The proposed algorithm, which adopts three FIB states and costs to enhance the maze routing, keeps at least one FIB candidate for each net while routing. Experimental results demonstrate that the proposed method can significantly increase the FIB observable rate under 100% routability.
15:30	IP5-13, 244	FUNCTIONAL TEST GENERATION GUIDED BY STEADY-STATE PROBABILITIES OF ABSTRACT DESIGN Speakers: Jian Wang1, Huawei Li2, Tao Lv2, Tiancheng Wang2 and Xiaowei Li2 1Institute of Computing Technology, Chinese Academy of Sc iences, CN; 2Institute of Computing Technology, Chinese Academy of Sciences, CN Abstract This paper presents a novel method for functional test generation aiming at exploring control state space of the design. The steady-state probabilities (SP's) of the abstract design's control FSM are used to guide test generation. The SP's of the states can reflect how hard the states can be reached, and the hard-to-reach states are assigned with high priority to be exercised. Experimental results show that our method has better performance in test generation in comparison with constrained random simulation, and demonstrate that SP's provide good guidance on traversing hard-to-reach states of the design under validation.
15:31	IP5-14, 991	AUTOMATED SYSTEM TESTING USING DYNAMIC AND RESOURCE RESTRICTED CLIENTS Speakers: Mirko Caspar, Mirko Lippmann and Wolfram Hardt, Technische Universität Chemnitz, DE Abstract Testing on system level using a static and homogeneous architecture of clients is common practice. This paper introduces a new approach to use a heterogeneous and dynamic set of resource restricted test clients for automated testing. Due to changing resources and availability of the clients, the test case distribution needs to be recalculated dynamically during the test execution. All necessary conditions and parameters are represented by a formal model. It is shown that the algorithmic problem of DYNAMIC TESTPARTITIONING can be solved in polynomial time by a heuristic recursive algorithm. A testbench architecture is introduced and by simulation it is shown that the testbench can execute the test requirements within a small variation using a number of several hundred clients. The system can react dynamically on changing resources and availability of the test clients within several seconds. The approach is generic and can be adapted to a huge number of systems.
15:30		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).