Date: Thursday 27 March 2014
Time: 14:00 - 15:30
Location / Room: Konferenz 1

Chair:
Emil Matus, Technische Universität Dresden, DE

Co-Chair:
Norbert Wehn, TU Kaiserslautern, DE

This session addresses various aspects of system modeling, synthesis, validation and verification with the strong focus on industrial relevance.

Time	Label	Presentation Title Authors
14:00	11.3.1	THE METAMODELING APPROACH TO SYSTEM LEVEL SYNTHESIS Speakers: Wolfgang Ecker1, Michael Velten1, Leily Zafari1 and Ajay Goyal2 1Infineon Technologies, DE; 2Infineon Technologies, IN Abstract This paper presents an industry proven Metamodeling based approach to System-Level-Synthesis which is seen as generic design automation strategy above today's implementation levels RTL (for digital) and Schematic Entry (for analog). The approach follows a new synthesis paradigm: The designer develops a simple domain and/or design specific language and a smart tool synthesizing implementation level models according to its needs. The overhead of making both a tool and a model pays off since the tool building is automated by code generation and reuse, both based on Metamodeling techniques. Also the focus on owns demand keeps development costs low. Finally, utilization of specification data keeps also modeling effort low and increases design consistency and thus decreases debug time. Using these concepts, single design steps have been speed up to a factor of 20x and implementations of chips (specification-to-tapeout) have been speed up to a factor of 3x.
14:15	11.3.2	LOGIC SYNTHESIS OF LOW-POWER ICS WITH ULTRA-WIDE VOLTAGE AND FREQUENCY SCALING Speakers: Yu Pu, Juan Echeverri, Maurice Meijer and Jose Pineda de Gyvez, NXP Research, NL Abstract For low-power digital ICs with ultra-wide voltage and frequency scaling (e.g., from the nominal supply voltage to the sub/near-threshold regime), achieving design closure can be a big challenge, especially when speed limits are pushed at very different voltages. This paper shares a practical logic synthesis recipe that helps to fulfill tight timing constraints. Our method includes: i) synthesizing circuits at a high voltage; ii) over-constraining maximal transition time; iii) pruning standard cell library based on cell delay degradation factor across voltages. This approach shows effectiveness on an industrial 90nm low-power micro-controller.
14:30	11.3.3	FORMAL VERIFICATION OF TAINT-PROPAGATION SECURITY PROPERTIES IN A COMMERCIAL SOC DESIGN Speakers: Pramod Subramanyan1 and Divya Arora2 1Princeton University, US; 2Intel Corporation, US Abstract SoCs embedded in mobile phones, tablets and other smart devices come equipped with numerous features that impose specific security requirements on their hardware and firmware. Many security requirements can be formulated as taint-propagation properties that verify information flow between a set of signals in the design. In this work, we take a tablet SoC design, formulate its critical security requirements as taint-propagation properties, and prove them using a formal verification flow. We describe the properties targeted, techniques to help the verifier scale, and security bugs uncovered in the process.
14:45	11.3.4	EARLY DESIGN STAGE THERMAL EVALUATION AND MITIGATION: THE LOCOMOTIV ARCHITECTURAL CASE Speakers: Tanguy Sassolas1, Chiara Sandionigi1, Alexandre Guerre2, Alexandre Aminot1, Pascal Vivet3, Hela Boussetta4, Luca Ferro4 and Nicolas Peltier4 1CEA, LIST, FR; 2CEA LIST, FR; 3CEA-LETI, FR; 4DOCEA Power, FR Abstract To offer more computing power to modern SoCs, transistors keep scaling in new technology nodes. Consequently, the power density is increasing, leading to higher thermal risks. Thermal issues need to be addressed as early as possible in the design flow, when the optimization opportunities are the highest. For early design stages, architects rely on virtual prototypes to model their designs' behavior with an adapted trade-off between accuracy and simulation speed. Unfortunately, accurate virtual prototypes fail to encompass thermal effects timescale. In this paper, we demonstrate that less accurate high-level architectural models, in conjunction with efficient power and thermal simulation tools, provide an adapted environment to analyze thermal issues and design software thermal mitigation solutions in the case of the Locomotiv MPSoC architecture.
15:00	11.3.5	MULTI-DISCIPLINARY INTEGRATED DESIGN AUTOMATION TOOL FOR AUTOMOTIVE CYBER-PHYSICAL SYSTEMS Speakers: Arquimedes Canedo1, Mohammad Abdullah Al Faruque2 and Jan Richter1 1Siemens Corporation, US; 2University of California Irvine, US Abstract This paper presents our multi-year experience in the development of a Functional Modeling Compiler (FMC), a new model-based design tool for the development of multi-disciplinary automotive cyber-physical systems. We show how system-level simulation models suitable for design-space exploration of complex architectures can be synthesized from functional specifications to test and validate the interactions between ECUs, control algorithms, and the multi-physics.
15:15	11.3.6	PREDICTIVE PARALLEL EVENT-DRIVEN HDL SIMULATION WITH A NEW POWERFUL PREDICTION STRATEGY Speakers: Seiyang Yang1, Jaehoon Han1, Doowhan Kwak1, Namdo Kim2, Daeseo Cha2, Junhyuck Park2 and Jay Kim2 1Pusan National University, KR; 2Samsung Electronics Co., KR Abstract Traditional parallel event-driven HDL simulation methods suffer heavy synchronization & communication overhead for timely transferring the signal data among local simulators, which could easily nullify most of the expected simulation speed-up from parallelization. A new predictive parallel event-driven HDL simulation as a new promising approach had been proposed for enhancing simulation performance. In this paper, we have further enhanced this noble parallel simulation method for a series of not only timing, but also function oriented design changes with a new powerful prediction strategy. Experimentation with real SOC designs from industry has been performed for actual design changes, and shown the effectiveness of the enhanced approach.
15:30		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).