Date: Thursday 27 March 2014
Time: 14:00 - 15:30
Location / Room: Konferenz 6

Chair:
Masoud Daneshtalab, University of Turku, FI

Co-Chair:
Hiroki Matsutani, Keio University, JP

The first paper of the session presents an approach to tolerating faults in NoCs through runtime reconfiguration, which is of increasing importance. The second paper focuses on management of thermal behaviour in NoCs to improve the reliability of optical communication given the tight tolerances of silicon photonics. Finally, the third paper also provides an outlook on optical NoCs by contrasting their properties against those of aggressive electrical baselines, to provide directions for future research in the field.

Time	Label	Presentation Title Authors
14:00	11.2.1	(Best Paper Award Candidate) BRISK AND LIMITED-IMPACT NOC ROUTING RECONFIGURATION Speakers: Doowon Lee, Ritesh Parikh and Valeria Bertacco, University of Michigan, US Abstract The expected low reliability of the silicon substrate at upcoming technology nodes presents a key challenge for digital system designers. Networks-on-chip (NoCs) are especially concerning because they are often the only communication infrastructure for the chips in which they are deployed. Recently, routing reconfiguration solutions have been proposed to address this problem. However, they come at a high silicon cost, and often require suspending the normal network activity while executing a centralized, resource-hungry reconfiguration algorithm. This paper proposes a novel, fast and minimalistic routing reconfiguration algorithm, called BLINC. BLINC utilizes precomputed routing metadata to quickly evaluate localized detours upon each fault manifestation. We showcase the efficacy of our algorithm by deploying it in a novel NoC fault detection and reconfiguration solution, where BLINC enables uninterrupted NoC operation during aggressive online testing. If a fault seems likely to occur, we circumvent it in advance with the aid of our BLINC reconfiguration algorithm. Experimental results show an 80% reduction in the average number of routers affected by a reconfiguration event, compared to state-of-the-art techniques. BLINC enables negligible performance degradation in our detection and reconfiguration solution, while solutions based on current techniques suffer a 17-fold latency increase.
14:30	11.2.2	THERMAL MANAGEMENT OF MANYCORE SYSTEMS WITH SILICON-PHOTONIC NETWORKS Speakers: Tiansheng Zhang, José L. Abellán, Ajay Joshi and Ayse K. Coskun, Boston University, US Abstract Silicon-photonic network-on-chips (NoCs) provide high bandwidth density; therefore, they are promising candidates to replace electrical NoCs in manycore systems. The silicon-photonic NoCs, however, are sensitive to the temperature gradients that typically occur on the chip, and hence, require proactive thermal management. This paper first provides a design space exploration of silicon-photonic networks in manycore systems and quantifies the performance impact of the temperature gradients for various network bandwidths. The paper then introduces a novel job allocation technique that minimizes the temperature gradients among the ring modulators/filters to improve the application performance. Experimental results for a single-chip 256-core system demonstrate that our policy is able to maintain the maximum network bandwidth. Compared to existing workload allocation policies, the proposed policy improves system performance by up to 26.1% when running a single application and 18.3% for multi-program scenarios.
15:00	11.2.3	ASSESSING THE ENERGY BREAK-EVEN POINT BETWEEN AN OPTICAL NOC ARCHITECTURE AND AN AGGRESSIVE ELECTRONIC BASELINE Speakers: Luca Ramini1, Paolo Grani2, Herve Tatenguem Fankem1, Alberto Ghiribaldi1, Sandro Bartolini2 and Davide Bertozzi1 1Engineering Department of the University of Ferrara, IT; 2University of Siena, IT Abstract Many crossbenchmarking results reported in the open literature raise optimistic expectations on the use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication. However, most of those previous works ultimately fail to make a compelling case for chip-level nanophotonic NoCs, especially for the lack of aggressive electronic baselines (ENoC), and the poor accuracy in physical- and architecture-layer analysis of the ONoC. This paper aims at providing the guidelines and minimum requirements so that nanophotonic emerging technology may become of practical relevance. The key differentiating factor of this work consists of contrasting ONoC solutions with an aggressive ENoC architecture with realistic complexity, performance, and power figures, synthesized on an industrial 40nm low-power technology. At the same time, key physical design issues and network interface architecture requirements for the ONoC under test are carefully assessed, thus paving the way for a well-grounded definition of the requirements for the emerging ONoC technology to achieve the energy break-even point with respect to pure electronic interconnect solutions in future multi- and many-core systems.
15:30	IP5-11, 618	DCM: AN IP FOR THE AUTONOMOUS CONTROL OF OPTICAL AND ELECTRICAL RECONFIGURABLE NOCS. Speakers: Wolfgang Büter1, Christof Osewold1, Daniel Gregorek1 and Alberto Garcia-Ortiz2 1University of Bremen, DE; 2ITEM (U.Bremen), DE Abstract The increasing requirements for bandwidth and quality-of-service motivate the use of parallel interconnect architectures with several degrees of reconfiguration. This paper presents an IP, called Distributed Channel Management (DCM), to extend existing packet-switched NoCs with a reconfigurable point-to-point network seamlessly, i.e., without the need for any modification on the routers. The configuration of the reconfigurable network takes place dynamically and autonomously, so that the topology can be changed at run time. Furthermore, the architecture is scalable due to the autonomous decentralized administration of the links. The Paper reports a thorough experimental analysis of the overhead of the approach at the gate level that considers different network parameters such as flit size and timing constraints.
15:31	IP5-12, 726	MINIMALLY BUFFERED SINGLE-CYCLE DEFLECTION ROUTER Speakers: Gnaneswara Rao Jonna1, John Jose1, Rachana Radhakrishnan2 and Madhu Mutyam1 1Indian Institute of Technology, Madras., IN; 2Rajagiri School of Engineering & Technology, Kochhi., IN Abstract With the drift from computation centric designs to communication centric designs in the Chip Multi Processor (CMP) era, the interconnect fabric is gaining more importance. An efficient NoC in terms of power, area and average flit latency has a huge impact on the overall performance of a CMP. In the current work, we propose MinBSD - a minimally buffered, single cycle, deflection router. It incorporates different operations (Injection, Ejection, Preemption, Re-injection) in a single module to handle the traffic effectively and ensures smooth flow of flits through router pipeline. It performs overlapped execution of independent operations. These factors not only make MinBSD to operate in a single cycle but also to reduce the critical path latency resulting in a faster interconnect network. Experimental results show that MinBSD reduces the average flit latency on real work loads, reduces die area and power consumption when compared to the existing state-of-the-art minimally buffered deflection routers.
15:30		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).