Date: Thursday 27 March 2014
Time: 14:00 - 15:30
Location / Room: Saal 1

Organisers:
Ian O'Connor, Lyon Institute of Nanotechnology, FR
Thomas Mikolajick, NamLab gGmbH, DE

Chair:
Aida Todri, LIRMM, FR

Co-Chair:
Thomas Mikolajick, NamLab gGmbH, DE

Alternative approaches to CMOS-based computing structures abound, for logic, memory, interconnect and interfaces. This embedded tutorial aims to give in-depth analyses of three promising technologies. The first paper covers spintronics and its use in logic and memory to achieve low-power computing architectures. Silicon photonics, with anticipated benefits for interconnect structures, is examined in the second paper. The third paper looks at the status of organic electronics and the properties of thin-film transistors for large displays and sensor arrays on flexible supports.

Time	Label	Presentation Title Authors
14:00	11.1.1	SPINTRONICS FOR LOW-POWER COMPUTING Speakers: Yue Zhang1, Weisheng Zhao1, Jacques-Olivier Klein1, Wang Kang1, Damien Querlioz1, Youguang Zhang2, Dafiné Ravelosona1 and Claude Chappert1 1IEF - Univ. Paris Sud, FR; 2Univ. Beihang, CN Abstract Microelectronics has been following Moore's law for almost 40 years. However this trend tends to run out of steam in recent technology nodes. The continuous improvements in the size of the transistors and in the operating frequencies result in serious power consumption, heat dissipation and reliability issues. Spintronics (Nobel Prize of Physics, 2007 awarded to Prof. Fert from Univ. Paris-Sud and Peter Grünberg from Forschungszentrum Jülich) nanodevices can reduce significantly the power, improve the reliability or allow new functionalities. The 2010 ITRS report on emerging research devices identified Magnetic Tunnel Junction (MTJ) nanopillar (the preeminent spintronics nanodevice) as one of the most promising technologies to be part of the future microelectronics circuits. It provides data non-volatility, hardness to radiations, fast data access and low-power operations. Magnetic memories become the most promising candidate for both low power logic computing and the data storage. This tutorial paper presents multi-discipline questions (Device, Circuit, Architecture, System and CAD) related to this topic to share the most recent results and discuss the future challenges.
14:30	11.1.2	CHAMELEON: CHANNEL EFFICIENT OPTICAL NETWORK-ON-CHIP Speakers: Sébastien Le Beux1, Hui Li1, Ian O'Connor1, Kazem Cheshmi2, Xuchen Liu1, Jelena Trajkovic2 and Gabriela Nicolescu3 1Lyon Institute of Nanotechnology, FR; 2Concordia University, CA; 3Ecole Polytechnique de Montréal, CA Abstract The next generation of MPSoC points to the integration of thousands of IP cores, requiring high performance interconnect for high throughput communications. Optical on-chip interconnect enables significantly increased bandwidth and decreased latency in MPSoC. However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability. In this paper, we propose a novel optical interconnect named CHAMELEON. The interface simplifies the layout and allows the bandwidth between IP cores to be adapted according to the communication requirements. Compared to related networks, CHAMELEON demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.
15:00	11.1.3	LOW-VOLTAGE ORGANIC TRANSISTORS FOR FLEXIBLE ELECTRONICS Speakers: Ute Zschieschang1, Reinhold Rödel1, Ulrike Kraft1, Kazuo Takimiya2, Tarek Zaki3, Florian Letzkus4, Jörg Butschke4, Harald Richter4, Joachim Burghartz4, Wei Xiong5, Boris Murmann5 and Hagen Klauk1 1Max Planck Institute for Solid State Research, DE; 2Riken Advanced Science Institute, JP; 3University of Stuttgart, DE; 4IMS CHIPS, DE; 5Stanford University, US Abstract A process for the fabrication of bottom-gate, top-contact (inverted staggered) organic thin-film transistors (TFTs) with channel lengths as short as 1 μm on flexible plastic substrates has been developed. The TFTs employ vacuum-deposited small-molecule semiconductors and a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs to operate with voltages of about 3 V. The p-channel TFTs have an effective field-effect mobility of about 1 cm2/Vs, an on/off ratio of 107, and a signal propagation delay (measured in 11-stage ring oscillators) of 300 ns per stage. For the n-channel TFTs, an effective field-effect mobility of about 0.06 cm2/Vs, an on/off ratio of 106, and a signal propagation delay of 17 μs per stage have been obtained.
15:30		End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).