Date: Thursday 27 March 2014
Time: 11:00 - 12:30
Location / Room: Konferenz 2

Chair:
Pablo Sanchez, University of Cantabria, ES

Co-Chair:
Florian Letombe, Synopsys, FR

The session presents system-level verification and simulation techniques, as well as specific solutions for particular system components. The first paper analyzes how to detect concurrency errors from multi-threaded software on a virtual platform. The second one proposes a hybrid simulation platform for cache configuration analysis. The last paper explores SSD verification challenges. The session is completed by three IPs that introduce novel approaches for parallel simulation and efficient NoC/Smart systems validation.

Time	Label	Presentation Title Authors
11:00	10.4.1	AUTOMATIC DETECTION OF CONCURRENCY BUGS THROUGH EVENT ORDERING CONSTRAINTS Speakers: Luis Gabriel Murillo, Simon Wawroschek, Jeronimo Castrillon, Rainer Leupers and Gerd Ascheid, RWTH Aachen University, DE Abstract Writing correct parallel software for modern multi-processor systems-on-chip (MPSoCs) is a complicated task. Programmers can rarely anticipate all possible external and internal interactions in complex concurrent systems. Concurrency bugs originating from races and improper synchronization are difficult to understand and reproduce. Furthermore, traditional debug and verification practices for embedded systems lack support to address this issue efficiently. For instance, programmers still need to step through several executions until finding a buggy state or analyze complex traces, which results in productivity losses. This paper proposes a new debug approach for MPSoCs that combines dynamic analysis and the benefits of virtual platforms. All in all, it (i) enables automatic exploration of SW behavior, (ii) identifies problematic concurrent interactions, (iii) provokes possibly erroneous executions and, ultimately, (iv) detects concurrency bugs. The approach is demonstrated on an industrial-strength virtual platform with a full Linux operating system and real-world parallel benchmarks.
11:30	10.4.2	HARDWARE-BASED FAST EXPLORATION OF CACHE HIERARCHIES IN APPLICATION SPECIFIC MPSOCS Speakers: Isuru Nawinne, Josef Schneider, Haris Javaid and Sri Parameswaran, The University of New South Wales, AU Abstract Multi-level caches are widely used to improve the memory access speed of multiprocessor systems. Deciding on a suitable set of cache memories for an application specific embedded system's memory hierarchy is a tedious problem, particularly in the case of MPSoCs. To accurately determine the number of hits and misses for all the configurations in the design space of an MPSoC, researchers extract the trace first using Instruction set simulators and then simulate using a software simulator. Such simulations take several hours to months. We propose a novel method based on specialized hardware which can quickly simulate the design space of cache configurations for a shared memory multiprocessor system on an FPGA, by analyzing the memory traces and calculating the cache hits and misses simultaneously. We demonstrate that our simulator can explore the cache design space of a quad-core system with private L1 caches and a shared L2 cache, over a range of standard benchmarks, taking as less as 0.106 seconds per million memory accesses, which is up to 456 times faster than the fastest known software based simulator. Since we emulate the program and analyze memory traces simultaneously, we eliminate the need to extract multiple memory access traces prior to simulation, which saves a significant amount of time during the design stage.
12:00	10.4.3	SSDEXPLORER: A VIRTUAL PLATFORM FOR FINE-GRAINED DESIGN SPACE EXPLORATION OF SOLID STATE DRIVES Speakers: Lorenzo Zuolo1, Cristian Zambelli1, Rino Micheloni2, Salvatore Galfano3, Marco Indaco3, Stefano Di Carlo3, Paolo Prinetto3, Pirero Olivo1 and Davide Bertozzi1 1Università degli Studi di Ferrara, IT; 2PMC-Sierra, IT; 3Politecnico di Torino, IT Abstract Solid State Drives (SSDs) are gaining particular momentum in various frameworks such as multimedia, large data centers and cloud environments. Unfortunately, efficient CAD tools for SSD design space exploration able to assess the optimization of the device microarchitecture w.r.t. the target performance are still missing. This paper tries to close this gap by proposing SSDExplorer, a tool for fine-grained and fast design space exploration of SSD devices. SSDExplorer provides unprecedented insights into the architecture behavior and subcomponent interaction efficiency, while avoiding the need for the actual implementation of an FTL or of key hardware components. This is achieved by the introduction of suitable abstractions of the different components. This is confirmed by the thorough validation of SSDExplorer against a commercial SSD device.
12:30	IP5-5, 221	EFFICIENT SIMULATION AND MODELLING OF NON-RECTANGULAR NOC TOPOLOGIES Speakers: Ji Qi and Mark Zwolinski, University of Southampton, GB Abstract With increasing chip complexity, Networks-on-Chips (NoCs) are becoming a central platform for future on-chip communications. Many regular NoC architectures have been proposed to eliminate the communication bottlenecks of traditional bus-based networks. Non-rectangular and irregular architectures have also been proposed to increase performance. However, the complexity of designing custom non-rectangular networks leads to a rapid increase in design and verification times. To alleviate the conflict between performance and efficiency, this paper proposes a novel method that efficiently constructs virtual non-rectangular topologies on a mesh network by using time-regulated models to emulate irregular patterns. Data routings on virtual hexagonal and two irregular geometries validate the proposed method. An MPEG-4 decoder is used to exemplify the proposed method for media applications. Results analysis shows the virtual topologies emulated by the proposed method can provide precise timing and energy performance.
12:32	IP5-6, 520	MOVING FROM CO-SIMULATION TO SIMULATION FOR EFFECTIVE SMART SYSTEMS DESIGN Speakers: Franco Fummi1, Michele Lora2, Francesco Stefanni3, Dimitrios Trachanis4, Jan Vanhese4 and Sara Vinco2 1University of Verona, EDALab s.r.l., IT; 2University of Verona, IT; 3EDALab s.r.l., IT; 4Agilent Technologies, BE Abstract Design of smart systems needs to cover a wide variety of domains, ranging from analogue to digital, with power devices, micro-sensors and actuators, up to MEMS. This high level of heterogeneity makes design a very challenging task, as each domain is supported by specific languages, modeling formalisms and simulation frameworks. A major issue is furthermore posed by simulation, that heavily impacts the design and verification loop and that is very hard to be built in such an heterogeneous context. On the other hand, achieving efficient simulation would indeed make smart system design feasible with respect to budget constraints. This work provides a formalization of the typical abstraction levels and design domains of a smart system. This taxonomy allows to identify a precise role in the design flow for co-simulation and simulation scenarios. Moreover, a methodology is proposed to move from the co-simulated heterogeneity to a simulatable homogeneous representation in C++ of the entire smart system. The impact of heterogeneous or homogeneous models of computation is also examined. Experimental results prove the effectiveness of the proposed C++ generation for reaching high-speed simulation.
12:30		End of session Lunch Break in Exhibition Area Sandwich lunch