Date: Thursday 27 March 2014
Time: 11:00 - 12:30
Location / Room: Konferenz 6

Chair:
Giorgos Dimitrakopoulos, Democritus University of Thrace, GR

Co-Chair:
Valeria Bertacco, University of Michigan, US

This session comprises three papers devoted to studying different aspects of wireless NoC design and optimization. The first paper focuses on energy efficiency, by effectively tuning the transmission power of on-chip antennas. The second paper compares the performance and power of different routing algorithms for wireless NoCs, while the third paper explores the adoption of wireless NoCs in 3D chip designs.

Time	Label	Presentation Title Authors
11:00	10.2.1	AN ADAPTIVE TRANSMITTING POWER TECHNIQUE FOR ENERGY EFFICIENT MM-WAVE WIRELESS NOCS Speakers: Andrea Mineo1, Maurizio Palesi2, Giuseppe Ascia1 and Vincenzo Catania1 1University of Catania, IT; 2Kore University, IT Abstract Several emerging techniques have been recently proposed for alleviating the communication latency and the energy consumption issues in multi/many-core architectures. One of such emerging communication techniques, namely, WiNoC replaces the traditional wired links with the use of wireless medium. Unfortunately, the energy consumed by the RF transceiver (i.e., the main building block of a WiNoC), and in particular by its transmitter, accounts for a significant fraction of the overall communication energy. In this paper we propose a runtime tunable transmitting power technique for improving the energy efficiency of the transceiver in wireless NoC architectures. The basic idea is tuning the transmitting power based on the location of the recipient of the current communication. The integration of the proposed technique into two known WiNoC architectures, namely, iWise64 and McWiNoC resulted in an energy reduction of 43% and 60%, respectively.
11:30	10.2.2	PERFORMANCE EVALUATION OF WIRELESS NOCS IN PRESENCE OF IRREGULAR NETWORK ROUTING STRATEGIES Speakers: Paul Wettin, Jacob Murray, Ryan Kim, Xinmin Yu, Partha Pande and Deukhyoun Heo, Washington State University, US Abstract The millimeter (mm)-wave small-world wireless NoC (mSWNoC) is an enabling interconnect architecture to design high performance and low power multicore chips. As the mSWNoC has an overall irregular topology, it is extremely important to design suitable deadlock-free routing mechanisms for it. In this paper we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. In presence of the benchmarks considered, the variation in latency and energy dissipation is small. However, the network hotspot temperature can vary considerably depending on the exact routing strategy and the characteristics of the benchmark.
12:00	10.2.3	LOW-LATENCY WIRELESS 3D NOCS VIA RANDOMIZED SHORTCUT CHIPS Speakers: Hiroki Matsutani1, Michihiro Koibuchi2, Ikki Fujiwara2, Takahiro Kagami1, Yasuhiro Take1, Tadahiro Kuroda1, Paul Bogdan3, Radu Marculescu4 and Hideharu Amano1 1Keio University, JP; 2National Institute of Informatics, JP; 3University of Southern California, US; 4Carnegie Mellon University, US Abstract In this paper, we demonstrate that by inducing a certain fraction of randomness into wireless 3D NoCs (where CMOS wireless links are used for vertical inter-chip communication) we can reduce the communication latency when considering the physical constraints of 3D design space. Towards this end, we consider two cases, namely 1) replacing existing horizontal 2D links in a wireless 3D NoC with randomized shortcut NoC links and 2) enabling full connectivity via adding a randomized NoC layer to a wireless 3D system with no or partial horizontal connectivity. Consequently, the packet routing is optimized by exploiting both the existing and the newly added random NoC. Thus, by adding randomly wired shortcut NoCs to a wireless 3D system, one can strike a good balance between the modular design and the minimum randomness needed for achieving low-latency. Experimental results show that by adding a random NoC chip to wireless 3D CMPs without built-in horizontal NoCs we can reduce the communication latency by as much as 26.2% when compared to that of adding a 2D mesh NoC. Also, the application execution time and average flit transfer energy can also be improved accordingly.
12:30	IP5-1, 578	HYBRID WIRE-SURFACE WAVE ARCHITECTURE FOR ONE-TO-MANY COMMUNICATION IN NETWORK-ON-CHIP Speakers: Ammar Karkar1, Nizar Dahir1, Ra'ed Al-Dujaily2, Kenneth Tong3, Terrence Mak4 and Alex Yakovlev1 1School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, GB; 2General Systems Company, Baghdad - Iraq, IQ; 3Depart- ment of Electrical and Electronic Engineering, University College London, GB; 4Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong, CN Abstract Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and has satisfied different demands in terms of high performance and economical interconnect implementation. However, merely metal based NoC pursuit offers limited scalability with the relentless technology scaling, especially in one-to-many (1-to-M) communication. To meet the scalability demand, this paper proposes a new hybrid architecture empowered by both metal interconnects and Zenneck surface wave interconnects (SWI). This architecture, in conjunction with newly proposed routing and global arbitration schemes, avoids overloading the NoC and alleviates traffic hotspots compared to the trend of handling 1-to-M traffic as unicast. This work addresses the system level challenges for intra chip multicasting. Evaluation results, based on a cycle-accurate simulation and hardware description, demonstrate the effectiveness of the proposed architecture in terms of power reduction ratio of 2 to 12X and average delay reduction of 25X or more, compared to a regular NoC. These results are achieved with negligible hardware overheads.
12:31	IP5-2, 101	FAILURE ANALYSIS OF A NETWORK-ON-CHIP FOR REAL-TIME MIXED-CRITICAL SYSTEMS Speakers: Eberle A Rambo1, Alexander Tschiene1, Jonas Diemer1, Leonie Ahrendts1 and Rolf Ernst2 1Technische Universität Braunschweig, DE; 2TU Braunschweig, DE Abstract Multi- and many-core architectures using Networks-on-Chip (NoC) are being explored for use in real-time safety-critical applications for their performance and efficiency. Such systems must provide isolation between tasks that may present distinct criticality levels. The NoC is critical to maintain the isolation property as it is a heavily used shared resource. To meet safety-standard requirements, such architectures require a systematic evaluation of the effects of all possible failures such as in the form of a Failure Mode and Effects Analysis (FMEA). We present the results of a detailed system-level analysis of a typical real-time mixed-critical network-on-chip architecture. This comprises an FMEA and error effects classification regarding duration and isolation violation.
12:30		End of session Lunch Break in Exhibition Area Sandwich lunch