W09 IRT Nanoelec Workshop: Bridging the gap between semiconductor technologies and architecture design
This workshop will introduce IRT Nanoelec as a key player in Grenoble ecosystem by sharing results and vision on imaging solutions, photonic components and cyber security innovations.
W09.1 Introduction and Keynote
W09.1.1 IRT Nanoelec at a glance
- About the talk : The presentation will briefly introduce the workshop, the mission of Nanoelec, its members and activities. A specific highlight will be provided on projects and results that demonstrate how device technologies meet new applications through IC design and novel circuit architectures.
- About the speaker: Hughes Metras has been appointed director of the technological research institute IRT Nanoelec on September 1st, 2019. Previously, he was in charge of strategic partnerships for the US region where he established CEA Leti’s commercial office in 2011. He benefits from a technical background in Physics engineering (Ecole Centrale de Marseille) and holds an MBA from the University of Miami (Florida).
W09.1.2 IRT Nanoelec: how to combine multi-partner technology and application research in innovative technical fields, while getting concrete results in the end
- About the talk: IRT Nanoelec has been used by ST where consortium R&D is most appropriate, that is upstream domains for sharing risks when target application is not well defined. It has associated equipment makers, software vendors, academic labs, and system companies to get feedback from applications. IRT has proven flexible enough to re-target the initial goals for instance from data centric approach to sensor centric for silicon photonics. It has also achieved interesting results in imagers from its 3D integration program, which was initially devoted to memory/logic. ST is looking forward to renew similar successes in the upcoming configuration of the IRT.
- About the speaker: Dr. Thomas has held R&D management positions in the industry, during his 30-year carrier, both in semiconductor and application fields such as Optronics or environmental sensing. From 2009 to 2018, he was the Director of the “Centre Commun de Microelectronique de Crolles” a joint venture between CEA and ST, which had hosted much of the seminal work of FDSOI. He was also part of the teams which defined and defended the Minalogic competitive cluster (2005/2006) and the IRT Nanoelec project (2010/2011) for the Grenoble ecosystem. and he has proposed several of the pilot line projects aiming at establishing the FDSOI ecosystem in Europe. He is now with Europe and France Public Affairs.
W09.2 3D Integration
W09.2.1 3D Technologies and Architectures for High Performance Computing
- About the talk: In the context of High Performance Computing (HPC) and scientific computing, the never ending demand of pushing the system performances, targeting power efficient architecture, while reducing the system costs leads to propose disruptive integration schemes. Based on advanced 3D integration, Chiplet-based partitioning offers a cost-efficient heterogeneous integration of a Lego-based optimized HPC system, which is composed of computing chiplets using an advanced technology node, which are 3D stacked on a mature interposer technology node. Pushing the limits further, smart interposer using active circuits allows to add smart features, such as power management, chiplet interconnects, system IOs, and system-on-chip infrastructure. The proposed talk will cover the concept of chiplet-based partitioning, then will present in more details a 96-core architecture prototype composed of 6 chiplets 3D-stacked on a smart interposer, and the corresponding advanced 3D integration technology, including µ-bumps, TSV-middle, and chiplet staking.
- About the speaker: Pascal Vivet is Scientific Director of the Architecture, IC Design and Embedded Software Division in CEA Leti, Grenoble, France. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He participates to various TPC such as ASYNC, DATE, 3DIC, ISLPED conferences. He served as a member of the organizing committee of the 3D workshops series at DATE from 2013 to 2015, and to the D43D workshops since 2011. He has authored and co-authored more than 80 papers and holds several patents in the field of digital design. He co-authored a book chapter on “3D Integration in VLSI Circuits: Implementation Technologies and Applications”.
W09.2.2 Benefits of 3D stacking process for Event Based sensors
W09.2.3 CAD tool for Smart Imager
CB Coffee Break
W09.3.1 Driving photonic implementation through automation
W09.3.2 Leti versatile silicon photonics platform
W09.3.3 Enabling Technologies for Field Programmable Photonic Gated Arrays
W09.4 Cybersecurity Session
W09.4.1 Why is the Industrial IoT such a complex playground for cybersecurity?
Jacques Fournier is a senior scientist in hardware security at the CEA Leti. He is currently the head of the hardware security lab. Prior to that, he held several technical positions in the Security Lab of smart card manufacturer Gemalto between 2001 and 2009. Jacques obtained his “Habilitation” from the University of Limoges (FR), a PhD from the University of Cambridge (UK), an MSECE from Georgia Tech (USA) and an engineering degree from the French Grande Ecole Supélec.