DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

W03-P1 Cadence - BTU - Europractice Workshop - Generation and Implementation of an industry-grade ASSP core (Part 1)

Start
Thursday, 4 February 2021 11:00
End
Thursday, 4 February 2021 15:00
Organizer
Anton Klotz, Cadence Design Systems, Germany
Organizer
Michael Hübner, Brandenburg University of Technology Cottbus, Germany
Organizer
Florian Fricke, Brandenburg University of Technology Cottbus, Germany
Organizer
Marcus Binning, Cadence Design Systems, United Kingdom
Organizer
Chris Skinner, Cadence Design Systems, United Kingdom
Organizer
Charis Kalantzi, Cadence Design Systems, Germany
Organizer
Clive Holmes, Europractice, United Kingdom
Organizer
Loganathan Sabesan, Cadence Design Systems, United Kingdom
Organizer
Simone Fini, Cadence Design Systems, United Kingdom
Organizer
Aspasia Karanasiou, Cadence Design Systems, United Kingdom

Tensilica ASSP is offered by Cadence Design Systems in the framework of Tensilica University Program to universities. It is possible to create a model of a processor core and extend it with special commands which accelerate certain operations. After comparison of before-after optimization, the core is exported to RTL and then processed through a physical design flow using Cadence tools Genus and Innovus towards GDS.

During the workshop on the first day the attendees will explore Tensilica Fusion F1 core, extend it with a simple extension using the TIE language, and compare the performance increase. The optimized core will be streamed out to Verilog RTL. On the second day the attendees will perform synthesis, placement, clock synthesis, routing, timing optimization and streamout to GDS.

The workshop will include various hand-ons, which can be performed by attendees using cloud-based tools from Cadence Design Systems. Every attendee will receive personal account for performing the exercises. The cloud platform will be provided by Europractice.

The attendees will be able to earn a digital badge for attending the workshop and accomplishing the hand-on exercises.