Tensilica ASSP is offered by Cadence Design Systems in the framework of Tensilica University Program to universities. It is possible to create a model of a processor core and extend it with special commands which accelerate certain operations. After comparison of before-after optimization, the core is exported to RTL and then processed through a physical design flow using Cadence tools Genus and Innovus towards GDS.

During the workshop on the first day the attendees will explore Tensilica Fusion F1 core, extend it with a simple extension using the TIE language, and compare the performance increase. The optimized core will be streamed out to Verilog RTL. On the second day the attendees will perform synthesis, placement, clock synthesis, routing, timing optimization and streamout to GDS.

The workshop will include various hand-ons, which can be performed by attendees using cloud-based tools from Cadence Design Systems. Every attendee will receive personal account for performing the exercises. The cloud platform will be provided by Europractice.

The attendees will be able to earn a digital badge for attending the workshop and accomplishing the hand-on exercises.