M08 An industry approach to deploying deep learning network on FPGA

Start
Monday, 9 March 2020 14:00
End
Monday, 9 March 2020 18:00

 

Abstract

FPGAs provide a flexible and attractive edge platform for competitive deep learning accelerators that also support differentiating customization because of their increasing floating-point operation (FLOP) performance and their support for both sparse data and compact data types.

MATLAB and Simulink provide a rich environment for AI system design and deployment, with libraries of proven, specialized algorithms ready to use for specific applications. The environment enables a model-based design workflow for fast prototyping and implementation of the algorithms on heterogeneous embedded targets, such as FPGA or MPSoC. 

This tutorial introduces a new workflow enabled by new capabilities in MATLAB that bridges the gap between a pre-trained neural network and general-purpose FPGAs, providing a new approach for graduate students, researchers and engineers in AI technology development or system design to rapidly prototype and prove the concept of their designs or algorithms. You will learn in this seminar, through presentation and examples, how to easily deploy a pre-trained deep learning network on a general purpose FPGAs without writing VHDL code. Specifically, you will learn

  • How to design, train and customize neural network in MATLAB
  • How to select the data types in MATLAB for efficient deployment on FPGA
  • How to do speed and resource tradeoff for a specific FPGA platform
  • How to automatically generate the portable VHDL and Verilog code for the customized inference processor
  • How to use the provided interface functions to transfer data between the host MATLAB and the processor on FPGA
  • How to integrate the pre-trained neural network processor into a larger system with data pre-processing and post-processing components

Agenda 

14:00 - 14:45 Designing, training and customizing neural network with MATLAB – John Zhao

14:45 - 16:00 Generating optimized VHDL/Verilog code for the customized neural network processor and deploying on FPGA– John Zhao

16:00 - 16:30 Coffee Break

16:30 - 18:00 Profiling and debugging the neural network processor on FPGA using the interface between MATLAB and FPGA – John Zhao