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M06 CAD for SoC Security

Start
Monday, 1 February 2021 15:00
End
Monday, 1 February 2021 18:40
Speaker
Mark Tehranipoor, University of Florida, United States
Speaker
Farimah Farahmandi, University of Florida, United States

Growing complexity of system-on-chips (SoCs) and ever-increasing cost of IC fabrication have forced the semiconductor industry to shift from a vertical business model to a horizontal model. In this model, time-to-market and manufacturing costs are lowered through outsourcing and design reuse. To be more specific, SoC designers obtain licenses for third party intellectual property (3PIPs), design an SoC by integrating the 3PIPs with their in-house IPs, and then sometime outsource the SoC design to contract design houses, foundries and assemblies for synthesis, DFT insertion, GDSII development, fabrication, test and packaging. With most of these entities involved in design, manufacturing, integration, and distribution located across the globe, SOC design houses no longer have the ability to monitor the entire process, and ensure security and trust.

Further, designers are not knowledgeable about all vulnerabilities in the design, and the countermeasures to address them. Unfortunately, existing tools do not help with the alleviating the magnitude of the problem. The tools are developed to optimize designs against power, performance, and area, while security is completely ignored. In fact, in some cases, tools and designers unintentionally create vulnerability in a circuit through security-unaware design processes/practices. These issues and the lack of trust and control have led to a large number of vulnerabilities. Hence, it is imperative to develop computer-aided design (CAD) tools with security in mind to identify and address vulnerabilities through design life-cycle.
To protect the SoC from such vulnerabilities, academic and industry researchers have proposed many design-for-security and security assessment techniques e.g., information flow tracking, side channel leakage analysis, IP encryption, logic obfuscation, design-for-anti-counterfeit, etc. Some of these techniques are currently being evaluated by industry and are expected to be adopted in near future. However, recent literatures have pointed out to some of the limitations of these approaches. Therefore, it is crucial to have in-depth understanding of the security provided by different techniques and understand their limitations.

The goal of this tutorial is to present (i) the threat posed by each entity in the SoC supply chain, (ii) vulnerabilities during design process / life-cycle, (iii) CAD tools and methodologies for security assessment, (iv) Countermeasure tools and methodologies for each vulnerability, and (vi) challenges and research roadmap ahead.