IP5_4 Interactive Presentations

Date: Wednesday, 03 February 2021
Time: 10:30 - 11:00 CET
Virtual Conference Room: https://virtual21.date-conference.com/meetings/virtual/GfdMuDtRsmQm9Jfss

Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session

Label Presentation Title
Authors
IP5_4.1 HETEROKV: A SCALABLE LINE-RATE KEY-VALUE STORE ON HETEROGENEOUS CPU-FPGA PLATFORMS
Speaker:
Haichang Yang, Institute of Microelectronics, Tsinghua University, CN
Authors:
Haichang Yang1, Zhaoshi Li2, Jiawei Wang2, Shouyi Yin2, Shaojun Wei2 and Leibo Liu2
1Tsinghua Unversity, CN; 2Tsinghua University, CN
Abstract
In-memory key-value store (KVS) has become crucial for many large-scale Internet services providers to build high-performance data centers. While most of the state-of-the-art KVS systems are optimized for read-intensive applications, a wide range of applications have been proven to be insert-intensive or scan-intensive, which scale poorly with the current implementations. With the availability of FPGA-based smart NICs in data centers, hardware-aided and hardware-based KVS systems are gaining their popularity. In this paper, we present HeteroKV, a scalable line-rate KVS on heterogeneous CPU-FPGA platforms, aiming to provide high throughput in read-, insert- and scan-intensive scenarios. To achieve this, HeteroKV leverages a heterogeneous data structure consisting of a b+ tree, whose leaf nodes are cache-aware partitioned hash tables. Experiments demonstrate HeteroKV's high performance in all scenarios. Specifically, a single node HeteroKV is able to achieve 430M, 315M and 15M key-value operations per second in read-, insert- and scan-intensive scenarios respectively, which are more than 1.5x, 1.4x and 5x higher than state-of-the-art implementations.