DATE 2019 Best Papers
| • The DATE 2019 Best Papers | • Best Paper Award Nominations |
DATE Best Paper Awards
Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Franco Fummi, Ian O’Connor, Cristiana Bolchini and Valeria Bertacco and the following members: Philip Brisk, Andrea Calimera, Suhaib Fahmy, Frédéric Mallet, Ingo Sander, Ayse Kivilcim Coskun, Pascal Vivet, Jaume Abella, Georges Gielen, Tulika Mitra, Graziano Pravadelli, Dirk Ziegenbein.
The DATE 2019 best papers are:
D Track
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
Elham Cheshmikhani1, Hamed Farbeh1, Hossein Asadi1
1 Sharif University of Technology, 2 Amirkabir University of Technology
A Track
When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans
Xiaolong Guo1, Huifeng Zhu2, Yier Jin1, Xuan Zhang2
1University of Florida, 2Washington University in St. Louis
T Track
Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core
Ron Gabor1, Yiannakis Sazeides2, Arkady Bramnik2, Alexandros Andreou2, Chrysostomos Nicopoulos2, Yanfeng Li2, Karyofyllis Patsidis3, Dimitris Konstantinou3, Giorgos Dimitrakopoulos
1 Intel, 2 University of Cyprus, 3Democritus University of Thrace
E Track
Data Subsetting: A Data-Centric Approach to Approximate Computing
Younghoon Kim1, Swagath Venkataramani2, Nitin Chandrachoodan3, Anand Raghunathan1
1 Purdue University, 2 IBM T. J. Watson Research Center, 3Indian Institute of Technology Madras
D track
HotR: Alleviating Read/Write Interference with Hot Read Data Replication for Flash Storage
Suzhen Wu1, Weiwei Zhang1, Bo Mao1 and Hong Jiang2
1Xiamen University, 2University of Texas-Arlington
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design using Reinforcement Learning
Ke Wang1, Ahmed Louri1, Avinash Karanth2, Razvan Bunescu2
1George Washington University, 2Ohio University
fbPDR: In-depth combination of forward and backward analysis in Property Directed Reachability
Tobias Seufert, Christoph Scholl
University Freiburg
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs
Benjamin Fletcher1, Shidhartha Das2, Terrence Mark1
1University of Southampton, 2ARM Ltd.
Automated Activation of Multiple Targets in RTL Models using Concolic Testing
Yangdi Liu, Alif Ahmed, Prabhat Mishra
University of Florida
PINT: Polynomial in Temperature Decode Weights in a Neuromorphic Architecture
Scott Reid, Antonio Montoya, Kwabena Boahen
Stanford University
IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design
Shuo-Hui Wang, Yen-Yu Su, Guan-Hong Liou, Mark Po-Hung Lin
National Chung Cheng University
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators
Sheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang
National University of Defense Technology
"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design
Andrew Kahng, Uday Mallappa, Lawrence Saul, Shangyuan Tong
University of California San Diego
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
Elham Cheshmikhani1, Hamed Farbeh2, Hossein Asadi1
1Sharif University of Technology, 2Amirkabir University of Technology
KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation
Kaveh Shamsi1, Meng Li2, David Z. Pan2, Yier Jin1
1 University of Florida, 2 University of Texas, Austin
NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support
Weidong Cao, Xin He, Ayan Chakrabarti, Xuan Zhang
Washington University in St Louis
A track
Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms
Alessio Burrello1, Lukas Cavigelli1, Kaspar Schindler2, Luca Benini1, Abbas Rahimi1
1ETH Zurich, 2University Bern
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices
Yu-Huei Lin1, Tsung-Yi Ho1, Bing Li2, Ulf Schlichtmann2
1National Tsing Hua University, 2Technical University of Munich
When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans
Xiaolong Guo1, Huifeng Zhu2, Yier Jin1, Xuan Zhang2
1 University of Florida, 2 Washington University in St. Louis
T track
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
Pablo Saraza-Canflanca1, Javier Diaz-Fortuny2, Rafael Castro-Lopez1, Elisenda Roca1, Javier Martin-Martinez2, Rosana Rodriguez2, Montserrat Nafria2, Francisco Vidal Fernandez2
1Universidad de Sevilla, 2Universidad Autonoma de Barcelona
Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core
Ron Gabor1, Yiannakis Sazeides2, Arkady Bramnik1 , Alexandros Andreou2, Chrysostomos Nicopoulos2, Yanfeng Li2, Karyofyllis Patsidis3, Dimitris Konstantinou3, Giorgos Dimitrakopoulos3
1 Intel, 2 University of Cyprus, 3Democritus University of Thrace
E track
Better Late Than Never Verification of Embedded Systems After Deployment
Martin Ring1, Fritjof Bornebusch1, Christoph Lüth2, Robert Wille3, Rolf Drechsler2
1DFKI, 2DFKI and University of Bremen, 3Johannes Kepler University Linz
Data Subsetting: A Data-Centric Approach to Approximate Computing
Younghoon Kim1, Swagath Venkataramani2, Nitin Chandrachoodan3, Anand Raghunathan1
1Purdue University, 2IBM T. J. Watson Research Center, 3Indian Institute of Technology Madras
Exploiting System Dynamics for Resource-Efficient Automotive CPS Design
Leslie Maldonado1, Wanli Chang2, Debayan Roy3, Anuradha Annaswamy1, Dip Goswami4, Samarjit Chakraborty3
1Massachusetts Institute of Technology, 2University of York, 3Technical University of Munich, 4Eindhoven University of Technology
Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration
Sebastian Vogel1, Jannik Springer1, Andre Guntoro1, Gerd Ascheid2
1Robert Bosch GmbH, 2RWTH Aachen University