3.8 Industrial Design Methods and Tools: RISC-V

Session Start
Tue, 17:30
Session End
Tue, 18:20
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features industrial design methods and tools. It is open to conference delegates as well as to exhibition visitors.

Presentations

3.8.1 Andes RISC-V Processor IP Solutions

Start
17:30
End
17:55
Speaker
Florian Wohlrab, Andes Technology, Taiwan

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications.