DATE 2021 became a virtual conference due to the worldwide COVID-19 pandemic (click here for more details)

Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organizing Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organizing Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

 
 
 
 

12.8.3 POWER-PERFORMANCE-THERMAL TRADE-OFFS IN M3D-ENABLED MANYCORE CHIPS

Start
17:00
End
17:30
Speaker
Partha Pratim Pande, Washington State University, United States
Author
Shouvik Musavvir, Washington State University, United States
Author
Anwesha Chatterjee, Washington State University, United States
Author
Ryan Kim, Colorado State University, United States
Author
Daehyun Kim, Washington State University, United States
Author
Janardhan Rao Doppa, Washington State University, United States
Author
Partha Pratim Pande, Washington State University, United States

Monolithic 3D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic inter-tier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. This results in significant performance and energy-efficiency improvements in M3D-based systems. Moreover, the thin inter-layer dielectric (ILD) used in M3D provides better thermal conductivity compared to TSV-based solutions and eliminates the possibility of thermal hotspots. However, the fabrication of M3D circuits still suffers from several non-ideal effects. The thin ILD layer may cause electrostatic coupling between tiers. Furthermore, the low-temperature annealing degrades the top-tier transistors and bottom-tier interconnects. An NoC-based manycore design needs to consider all these M3D-process related non-idealities. In this paper, we discuss various design challenges for an M3D-enabled manycore chip. We present the power-performance-thermal trade-offs associated with these emerging manycore architectures.