Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organising Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organising Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

W09.2.1 3D Technologies and Architectures for High Performance Computing

  • About the talk: In the context of High Performance Computing (HPC) and scientific computing, the never ending demand of pushing the system performances, targeting power efficient architecture, while reducing the system costs leads to propose disruptive integration schemes. Based on advanced 3D integration, Chiplet-based partitioning offers a cost-efficient heterogeneous integration of a Lego-based optimized HPC system, which is composed of computing chiplets using an advanced technology node, which are 3D stacked on a mature interposer technology node. Pushing the limits further, smart interposer using active circuits allows to add smart features, such as power management, chiplet interconnects, system IOs, and system-on-chip infrastructure. The proposed talk will cover the concept of chiplet-based partitioning, then will present in more details a 96-core architecture prototype composed of 6 chiplets 3D-stacked on a smart interposer, and the corresponding advanced 3D integration technology, including µ-bumps, TSV-middle, and chiplet staking.
  • About the speaker: Pascal Vivet is Scientific Director of the Architecture, IC Design and Embedded Software Division in CEA Leti, Grenoble, France. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He participates to various TPC such as ASYNC, DATE, 3DIC, ISLPED conferences. He served as a member of the organising committee of the 3D workshops series at DATE from 2013 to 2015, and to the D43D workshops since 2011. He has authored and co-authored more than 80 papers and holds several patents in the field of digital design. He co-authored a book chapter on “3D Integration in VLSI Circuits: Implementation Technologies and Applications”.

URL: http://www.leti-cea.com/cea-tech/leti/english