W09.2 3D Integration
W09.2.1 3D Technologies and Architectures for High Performance Computing
- About the talk: In the context of High Performance Computing (HPC) and scientific computing, the never ending demand of pushing the system performances, targeting power efficient architecture, while reducing the system costs leads to propose disruptive integration schemes. Based on advanced 3D integration, Chiplet-based partitioning offers a cost-efficient heterogeneous integration of a Lego-based optimized HPC system, which is composed of computing chiplets using an advanced technology node, which are 3D stacked on a mature interposer technology node. Pushing the limits further, smart interposer using active circuits allows to add smart features, such as power management, chiplet interconnects, system IOs, and system-on-chip infrastructure. The proposed talk will cover the concept of chiplet-based partitioning, then will present in more details a 96-core architecture prototype composed of 6 chiplets 3D-stacked on a smart interposer, and the corresponding advanced 3D integration technology, including µ-bumps, TSV-middle, and chiplet staking.
- About the speaker: Pascal Vivet is Scientific Director of the Architecture, IC Design and Embedded Software Division in CEA Leti, Grenoble, France. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He participates to various TPC such as ASYNC, DATE, 3DIC, ISLPED conferences. He served as a member of the organizing committee of the 3D workshops series at DATE from 2013 to 2015, and to the D43D workshops since 2011. He has authored and co-authored more than 80 papers and holds several patents in the field of digital design. He co-authored a book chapter on “3D Integration in VLSI Circuits: Implementation Technologies and Applications”.
W09.2.2 Benefits of 3D stacking process for Event Based sensors
- About the talk: 3D stacking processes are very suitable for Image sensor with complex pixel structure composed of many components. During the talk, we will discuss the unique nature of event based sensor and the trade offs to optimize their design using 3D Stacking process. Long-term evolutions of the 3D integration for intelligent image sensor will also be discussed.
- About the speaker: Jean-Luc Jaffard has been graduated from Ecole Supérieure d’Electricité of Paris in 1979. From 1980 to 1996 he occupied various R&D management positions in consumer division of SGS Thomson Microelectronics (initially Thomson Semiconductor) From 1996 Jean-Luc Jaffard paved the way of imaging activity at STMicroelectronics being at the forefront of the emergence and growth of this business. At STMicroelectronics Imaging Division he was successively appointed Research Development and Innovation Director and later on promoted Deputy General Manager. In 2010 he was appointed STMicroelectronics Intellectual Property Business Unit Director. In 2014 he created the Technology and Innovation branch of Red Belt Conseil, bringing expertise in optimisation of complex and innovative solutions to develop competitive products. From 2014 he has been acting as SEMI Europe Imaging conference Chairman. In 2016 he joined Prophesee, French start-up developing biomorphic sensor and processing technology as VP Hardware