Taking into consideration the continued erratic development of the worldwide COVID-19 pandemic and the accompanying restrictions of worldwide travelling as well as the safety and health of the DATE community, the Organising Committees decided to host DATE 2021 as a virtual conference in early February 2021. Unfortunately, the current situation does not allow a face-to-face conference in Grenoble, France.

The Organising Committees are working intensively to create a virtual conference that gives as much of a real conference atmosphere as possible.

ET3.8.2 AI from Edge to Cloud: Leveraging RISC-V with DSP, Vector and Custom Instructions


In this talk, Andes Technology will present RISC-V processors for applications ranging from very compact, low power cores used in Sensors to mid-ranged cores in running protocol stacks and doing high-speed control, and number-crunching cores to process high-volume data in parallel. Those highly-configurable AndesCores™ with extensibility and modularity inherited from RISC-V allow designers to use one ISA for all of the workloads. They are also adopted by AI SoC’s with applications from edge to cloud. We will provide an overview of the RISC-V DSP extension for low-data volume workloads like Keyword Spotting and Face detection with low power. For higher data throughput applications, we will introduce the industry-first commercial RISC-V Vector Processor solution and how it can be used to speed up compute-intensive applications. Last but not least, one of RISC-V’s strength is to allow well-defined custom instruction extensions to fulfill Domain Specific Acceleration (DSA) without breaking ISA compatibility. In the end, we will also cover Andes Custom Extensions™, an automation framework to bring DSA capability to the hands of every designer instead of limiting it to just CPU experts.