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ET4.8.2 Scalable NoC, SoC and associated Testbench generation using Defacto STAR

Start
17:30
End
18:00

As part of the Mont Blanc 2020, European scalable, modular and power efficient HPC processor, ATOS designs and implement a NoC which includes NoC Xpoints, Protocol agents and system cache.

Our Network on Chip (NoC) is based on basic Xpoint modules which are connected to each other to make a scalable NoC. Each Xpoint module has :

  • 4 internal CHI Interface (1 per direction) where all the Xpoint modules are connected to
  • 2 End Points CHI Interface which are the entry/exit points of IPs on the System on Chip (Soc)

A CHI interface contains 4 channels interfaces: Request, Data, Snoop and Response. Each channel is fully configurable in each direction and is implemented with Configurable System Verilog Interface. This makes a lot of parameters to handle as we plan to implement an 8x8 NoC which includes 64 Xpoint modules with corresponding parameters set accordingly.

Defacto STAR tool is used to efficiently:

  • instantiate all the Xpoint modules with corresponding parameters
  • connect all the channels with corresponding System Verilog Interface
  • connect the Error, status and configuration interfaces
  • connect Protocol Agent on End Point interface (internally)
  • create NoC entity.

The main benefits to choose Defacto STAR is

  • NoC configuration change and RTL generation in 15 s
  • No need to develop our own tools

NoC module will then be integrated at SoC level and connected to IPs delivered by Third-parties. We also use Defacto STAR tool to generate the SoC RTL and associated Testbench.