ET3.8 Solutions for AI on Chip using Neuromorphic Hardware, for AI from Edge to Cloud and for Power-Efficiency

Session Start
Tue, 14:30
Session End
Tue, 16:00

DATE 2020 Exhibition Theatre leading experts provide attendees with their advice on the latest technologies in the field, covering applications as well as solutions for the design process. In this session Intel and Andes Technology will cover the implementation of AI highlighting neuromorphic hardware, RISC-V and AI from edge to cloud. Dolphin Design will show how to speed up the design of the required power-efficient SoC.

Presentations

ET3.8.1 AI on Chip: Perception, Learning, and Control in Neuromorphic Hardware

Start
14:30
End
15:00

Today, Artificial Intelligent systems are dominated by deep neuronal networks that learn to solve tasks from data. The DNNs have replaced computer vision architectures with hand-crafted features and have revolutionised data and signal processing. In order to train and run DNN architectures efficiently, specialised hardware accelerators are developed. One type of these accelerators is neuromorphic hardware, originally developed to emulate behaviour of biological neurons using electrical circuits. Modern neuromorphic devices such as Intel’s Loihi research chip directly execute spiking neuronal networks and often include plasticity — the ability of network connections to change on the fly based on local activity in the network. This hardware promises a new computing framework that goes beyond deep learning. These new computing framework features ultrafast event-based inference and one-shot learning — key capabilities to deploy DNNs in low-latency applications in dynamic environments. This talk will show how neuromorphic hardware can be used to solve robotic tasks. 

ET3.8.2 AI from Edge to Cloud: Leveraging RISC-V with DSP, Vector and Custom Instructions

Start
15:00
End
15:30

In this talk, Andes Technology will present RISC-V processors for applications ranging from very compact, low power cores used in Sensors to mid-ranged cores in running protocol stacks and doing high-speed control, and number-crunching cores to process high-volume data in parallel. Those highly-configurable AndesCores™ with extensibility and modularity inherited from RISC-V allow designers to use one ISA for all of the workloads. They are also adopted by AI SoC’s with applications from edge to cloud. We will provide an overview of the RISC-V DSP extension for low-data volume workloads like Keyword Spotting and Face detection with low power. For higher data throughput applications, we will introduce the industry-first commercial RISC-V Vector Processor solution and how it can be used to speed up compute-intensive applications. Last but not least, one of RISC-V’s strength is to allow well-defined custom instruction extensions to fulfill Domain Specific Acceleration (DSA) without breaking ISA compatibility. In the end, we will also cover Andes Custom Extensions™, an automation framework to bring DSA capability to the hands of every designer instead of limiting it to just CPU experts.

ET3.8.3 PMU design in weeks, not months: the need for SPEED

Start
15:30
End
16:15

Energy-efficiency has now replaced low-power as one of the biggest challenges that the semiconductor industry is facing. All vertical market segments are calling for more power-efficient applications, driven by a global need to reduce our environmental footprint and make the best use of energy sources. The emergence of smart cities, smart homes and smart buildings, enabled by billions of battery-operated IoT devices connected to data centers, will force the semiconductor industry to adopt disruptive approaches to improve the energy-efficiency of both edge and cloud devices.

When it comes to IC design, the traditional approaches for power reduction were mainly driven by Moore’s law and are now suffering from its slowdown, pushing SoC design teams to use more and more advanced SoC architecture and complex design techniques to overcome the fact that technology scaling is not sufficient anymore. As a consequence, the SoC complexity required to demonstrate the best energy-efficiency figures results in longer design cycles, higher development costs and additional risks.

Leveraging its SPEED Platform that reduces the PMU design time from months to weeks, Dolphin Design provides a turnkey solution to speed-up and secure the design of advanced power management solutions from SoC architecture to implementation. Energy-efficiency and low power designs are part of Dolphin’s DNA since its inception. In this presentation we will present how we work hand-in-hand with our customers to simplify the design of power-efficient SoC, allowing them to focus on their core competencies and added value.