Technical Programme Committee 2018

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Topic: T3 Design-for-Test, Test Infrastructures, Test Standards

Architectures and solutions for design for test, diagnosis, debug, post silicon validation; functional safety; in-system run-time test; BIST and embedded test; power-on self-test; test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, SoC, NoC, and microprocessors; ATE architectures; test standards (JTAG, IJTAG, 1500, 1687, P1838).

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Jerzy Tyszer, Poznan University of Technology, PL, Contact


  • Erik Larsson, Lund University, SE, Contact
  • Teresa McLaurin, ARM, US, Contact
  • Grzegorz Mrugalski, Mentor Graphics, PL, Contact
  • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact