Technical Programme Committee 2018

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Topic: T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

Chair: Mehdi Tahoori, Karlsruhe Institute of Technology, DE, Contact

Co-Chair: Said Hamdioui, Delft University of Technology, NL, Contact


  • Vikas Chandra, ARM, US, Contact
  • Saman Kiamehr, Bosch Starter Generator GmbH, DE, Contact
  • Bram Kruseman, NXP Semiconductors, NL, Contact
  • Hans Manhaeve, Ridgetop Europe, BE, Contact
  • Jose Pineda, NXP Semiconductors, NL, Contact
  • Rosa Rodríguez-Montañés, UPC, ES, Contact
  • Elena Ioana Vatajelu, TIMA, FR, Contact