Technical Programme Committee 2018

Printer-friendly version PDF version

Topic: D9 Power Modeling, Low-Power Design, and Power-Aware Optimization

Algorithms, techniques, and tools for modeling, estimating, or optimizing power consumption of electronic systems, applicable at all levels of the design (HW, SW, or system level), including: dynamic power management; leakage current minimization; design flows and circuit architectures for ultra-low power consumption; energy harvesting; battery modeling and design.

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, KAIST, KR, Contact


  • Paolo Amato, Micron, IT, Contact
  • Nadine Azemard, LIRMM, FR, Contact
  • Andrea Bartolini, University of Bologna, IT, Contact
  • Andrea Calimera, Politecnico di Torino, IT, Contact
  • Jae-Joon Kim, Pohang University of Science and Techology, KR, Contact
  • Hiroshi Nakamura, The University of TOKYO, JP, Contact
  • Alberto Nannarelli, Technical University, DK, Contact
  • Salvatore Rinaudo, STMicroelectronics, IT, Contact
  • Johanna Sepulveda, TU Munich, DE, Contact
  • Donghwa Shin, Department of Computer Engineering, Yeungnam University, KR, Contact
  • Sheldon Tan, University of California at Riverside, US, Contact
  • Pascal Vivet, CEA-Leti, FR, Contact
  • Yanzhi Wang, University of Southern California, US, Contact
  • Shusuke Yoshimoto, Osaka University, JP, Contact