Technical Programme Committee 2018

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Topic: D7 Network on Chip

Architecture, design methodologies, and modeling techniques for NoC, including: topology, switching, routing and flow control; NoC service frameworks for Quality-of-Service, security, and power management; techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; integration of external interfaces or memory controllers with NoCs; cache-coherent NoCs; HW-SW communication abstractions; component-based modeling; platform-based design and methodologies; NoC design space exploration frameworks; programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

Chair: Luca Carloni, Columbia University, US, Contact

Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact


  • Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact
  • Ravi Iyer, Intel, US, Contact
  • Axel Jantsch, TU Wien, AT, Contact
  • Ajay Joshi, Boston University, US, Contact
  • John Kim, KAIST, KR, Contact
  • Romain Lemaire, CEA-Leti, FR, Contact
  • Fernando Moraes, PUCRS University, BR, Contact
  • Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA, Contact
  • Li-Shiuan Peh, Professor, National University of Singapore, SG, Contact
  • Jiang Xu, Hong Kong University of Science and Technology, HK, Contact
  • Davide Zoni, Politecnico di Milano, IT, Contact