Technical Programme Committee 2018

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Topic: D3 System Simulation and Validation

Simulation-based and semi-formal validation and verification of SoCs, MPSoCs, and emerging architectures at any level (from system to circuits), including digital, analog, interconnect or mixed-signal components; testbench and assertion generation and qualification; checker synthesis and optimization; multi-domain and mixed-critical simulation techniques; acceleration-driven and emulation-based approaches for verification and validation; simulation-based pre- and post-silicon diagnosis and debugging solutions; validation and verification for IoT and cloud infrastructures; validation and verification using artificial intelligence or machine learning techniques.

Chair: Valeria Bertacco, University of Michigan, US, Contact

Co-Chair: Graziano Pravadelli, EDALab, IT, Contact

Members:

  • Anupam Chattopadhyay, Nanyang Technological University, SG, Contact
  • Flavio M. de Paula, IBM Corporation, US, Contact
  • Daniel Grosse, University of Bremen/DFKI, DE, Contact
  • Florian Letombe, Synopsys, FR, Contact
  • Katell Morin-Allory, TIMA Laboratory, FR, Contact
  • Jaan Raik, Tallinn university of Technology, EE, Contact
  • Sandip Ray, Intel Corporation, US, Contact
  • Daniel Schostak, ARM Ltd, GB, Contact
  • Shobha Vasudevan, UIUC, US, Contact
  • Sara Vinco, Politecnico di Torino, IT, Contact
  • Li-C. Wang, UCSB, US, Contact