Technical Programme Committee 2018

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Topic: D2 System Design, High-Level Synthesis, and Optimization

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact


  • Lars Bauer, Karlsruhe Institute of Technology, DE, Contact
  • Kiyoung Choi, Seoul National University, KR, Contact
  • Michael Glaß, Ulm University, DE, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Luciano Lavagno, Politecnico di Torino, IT, Contact
  • David Novo, French National Centre for Scientific Research (CNRS), FR, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • Donatella Sciuto, Politecnico di Milano, IT, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • jason xue, City University of Hong Kong, HK, Contact
  • Daniel Ziener, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact