Technical Programme Committee 2018

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Topic: D12 Logical and Physical Analysis and Design

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT, Contact

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact


  • Luca Amaru, Synopsys, US, Contact
  • Anna Bernasconi, Universita' di Pisa, IT, Contact
  • Luca Daniel, M.I.T., US, Contact
  • Patrick Groeneveld, DAC, US, Contact
  • Igor L. Markov, University of Michigan, US, Contact
  • Jose Monteiro, INESC-ID, T├ęcnico, U Lisboa, PT, Contact
  • Rajeev Murgai, Synopsys India Pvt. Ltd., IN, Contact
  • Farhana Sheikh, Intel Corporation, US, Contact
  • Mathias Soeken, EPFL, CH, Contact
  • Wenjian Yu, Tsinghua University, CN, Contact